User Manual - Terasic

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1.2 About the KITThe kit comes with the following contents:• DE0-Nano board• System CD-ROM.• USB CableThe system CD contains technical documents for the DE0-Nano board, which includes componentdatasheets, demonstrations, schematic, and user manual.Figure 1-2 shows the photograph of the DE0-Nano kit contents.Figure 1-2 DE0-Nano kit package contents1.3 Getting HelpHere is information of how to get help if you encounter any problem:• <strong>Terasic</strong> Technologies• Tel: +886-3-575-0880• Email: support@terasic.com• Altera Corporation• Email: university@altera.com6
Page 4 and 5: Chapter 1IntroductionThe DE0-Nano b
Page 8 and 9: Figure 2-2 The DE0-Nano Board PCB a
Page 10 and 11: Chapter 3Using the DE0-Nano BoardTh
Page 15 and 16: DRAM_ADDR[12] PIN_L4 SDRAM Address[
Page 17 and 18: Figure 3-8 Pin arrangement of the G
Page 19 and 20: GPIO_17 PIN_T11 GPIO Connection DAT
Page 21 and 22: Figure 3-12 Pin1 locations of the 2
Page 23 and 24: Figure 3-14 Block diagram of the cl
Page 25 and 26: Chapter 4DE0-Nano Control PanelThe
Page 27 and 28: Figure 4-2 The DE0-Nano Control Pan
Page 29 and 30: Figure 4-5 Accessing the SDRAMA 16-
Page 31 and 32: Figure 4-6 Digital Accelerometer st
Page 33 and 34: Chapter 5DE0-Nano System BuilderThi
Page 35 and 36: 5.3 Using DE0-Nano System BuilderTh
Page 37 and 38: • GPIO ExpansionUsers can connect
Page 39 and 40: Chapter 6Tutorial: Creating an FPGA
Page 41 and 42: Figure 6-2 Found New Hardware Wizar
Page 43 and 44: Figure 6-5 Browse to find the locat
Page 45 and 46: 1. In the Quartus II software, sele
Page 47 and 48: Figure 6-10 Specify the Device Exam
Page 51 and 52: Figure 6-14 Saving the Verilog HDL
Page 53 and 54: 9. Right click in the blank area of
Page 55 and 56: 3. Click Next.4. In MegaWizard Plug
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Figure 6-22 MegaWizard Plug-In Mana
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Figure 6-24 Wizard-Created FilesThe
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Figure 6-27 Draw a Bus Line connect
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Figure 6-30 Change the input port n
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1. Right click in the blank area of
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Figure 6-35 lpm_mux Symbol13. Click
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Figure 6-38 Choose output pin18. Cl
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Figure 6-41 Pin Planner Example2. I
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Figure 6-43 Default SDCNaming the S
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Figure 6-45 Compilation Report Exam
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Figure 6-47 Hardware Setting4. Clic
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Figure 6-49 Device and OptionsSelec
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Chapter 7Tutorial: Creating a Nios
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Figure 7-3 Input the working direct
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Figure 7-6 New Project Wizard: EDA
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Figure 7-10 Create New SOPC System
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Figure 7-14 Add NIOS II Processor89
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Figure 7-16 Add Nios II CPU complet
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11. Add a second component by selec
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Figure 7-21 JTAG UART13. Select the
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Figure 7-23 Add On-Chip Memory97
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Figure 7-25 Update Total memory siz
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Figure 7-28 Update CPU settings101
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Figure 7-30 Add PIO103
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Figure 7-32 PIO21. Rename pio_0 to
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23. Click the Generate button, whic
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25. Create a new Verilog HDL file,
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Figure 7-44 and Figure 7-45.module
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Figure 7-45 DE0_NANO_SOPC module35.
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37. A dialog box will appear upon s
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7. Click Change File.8. Browse to t
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7.4 Create a hello_world Example Pr
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Figure 7-56 Nios II IDE C++ Project
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After a successful compilation, rig
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7.7 Why the LED BlinksThe Nios II s
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5. Select Run > Resume to resume ex
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Chapter 8DE0-Nano Demonstrations8.1
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8.3 ADC ReadingThis demonstration i
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Figure 8-4 2X13 Header• System Re
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8.4 SOPC DemoThis demostration illu
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The data format is configured as 10
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Demonstration Source Code• Projec
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8.5 G-SensorThis demonstration illu
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Chapter 9Appendix9.1 Programming th
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Figure 9-2 Highlight Flash Loader11
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Figure 9-4 Convert Programming File
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2. Program the serial configuration
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9.2 EPCS Programming via nios-2-fla
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User Manual - Terasic

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