User Manual - Terasic
User Manual - Terasic
User Manual - Terasic
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always @ (posedge CLOCK_5)// on positive clock edgebegincounter_out Save, pressing Ctrl + S, or by clicking the floppy disk icon.6. Select File > Create/Update > Create Symbol Files for Current File to convert thesimple_counter.v file to a Symbol File (.sym). You will use this Symbol File to add the HDL codeto your schematic.The Quartus II software creates a Symbol File and displays a message (see Figure 6-16).Figure 6-16 Create Symbol File was Successful7. Click OK.8. To add the simple_counter.v symbol to the top-level design, click the my_first_fpga.bdf tab.52