User Manual - Terasic

The data format is configured as 10 bits, right-justify, +/- 2g mode. The output data rate isconfigured as 400 HZ. The X/Y/Z value is read using polling mode. Before reading X/Y/Z, themaster needs to make sure data is ready by reading the register 0x30-INT_SOURCE, as shownbelow Figure 8-9, and checking the DATA_READY bit. In the demo, multiple-byte read of sixbytes X/Y/Z, register from 0x32 to 0x37, is performed to prevent a change in data between reads ofsequential register. Note, the output data is twos complement with DATAx0 as the least significantbyte and DATAx1 as the most significant byte, where x represent X, Y, or Z.Figure 8-9 Register 0x30The SPI timing scheme follows clock polarity (CPOL)=1 and clock phase (CPHA)=1. (CPOL)=1means the clock is high in idle. (CPHA)=1 means data is captured on clock’s rising edge and data ispropagated on a falling edge. The timing diagram of 3-wire SPI is shown below Figure 8-10:Figure 8-10 3-wire SPI Timing Diagram• ADC ControlThe Analog to Digital Conversion is controller through a 4-wire SPI interface with the timing dialoggiven below Figure 8-11. Note, the DIN signal is used to specify the channel (IN0~IN7) for thenext data conversion. The DOUT signal is used to read the data conversion result whose channel isspecified in previous transaction. The first conversion result after power-up will be on IN0. Theoutput format of conversion result is straight binary.137