User Manual - Terasic

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Figure 9-1 Convert Programming Files Dialog Box144
Figure 9-2 Highlight Flash Loader11. Select the targeted FPGA, Cyclone IV E EP4CE22, as shown in Figure 9-3.12. Click OK. The Convert Programming Files page displays, should look like Figure 9-4.13. Select the .sof file, and Click the Properties. Select Compression, click OK, as shown inFigure 9-5.14. Click Generate.145
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Chapter 1IntroductionThe DE0-Nano b
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1.2 About the KITThe kit comes with
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2.3 Power-up the DE0-Nano BoardThe
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Figure 3-1 Programming a serial con
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Figure 3-7 Connections between FPGA
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GPIO_03 PIN_A3 GPIO Connection DATA
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Figure 3-10 Pin distribution of the
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3.7 Digital AccelerometerThe ADXL34
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• Power Distribution SystemFigure
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8. The Control Panel is now ready f
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4.3 Switches and PushbuttonsChoosin
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The Sequential Read function is use
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4.7 Overall Structure of the DE0-Na
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The generated system is described u
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Figure 5-3 The DE0-Nano Board Type
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Figure 5-6 Project Settings• Proj
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6.2 Before You BeginThis tutorial a
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The driver is available within the
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The driver will now be installed as
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Figure 6-9 Project informationd. Cl
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Figure 6-11 my_first_fpga project6.
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always @ (posedge CLOCK_5)// on pos
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14. Press the Esc key or click an e
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d. Click Next.Figure 6-21 MegaWizar
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Figure 6-23 MegaWizard Plug-In Mana
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Figure 6-25 PLL Symbol11. Click OK
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4. Place the new pin onto the BDF s
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Figure 6-31 Change the output BUS n
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Figure 6-34 lpm_mux settings9. Clic
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15. Add input buses and output pins
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Figure 6-40 Adding the KEY [0] Inpu
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Figure 6-42 Completed Pin Planning
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Figure 6-44 Compilation Message for
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Figure 6-46 Programmer Window2. Cli
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Figure 6-48 Downloading CompleteCon
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Figure 6-50 Setting unused pinsClic
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Figure 7-1 Start to Create a New Pr
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Figure 7-5 New Project Wizard: Fami
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Figure 7-8 A New Complete Project5.
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Figure 7-12 Create New System[2]7.
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Figure 7-15 Nios II Processor9. Cli
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Figure 7-17 Rename the CPU (1)Figur
Page 94 and 95: Figure 7-20 JTAG UART’s add wizar
Page 96 and 97: Figure 7-22 Rename JTAG UART15. Add
Page 98 and 99: Figure 7-24 On-Chip Memory Box16. M
Page 100 and 101: Figure 7-26 Add On-Chip memory17. R
Page 102 and 103: Figure 7-29 Updated CPU settings19.
Page 104 and 105: Figure 7-31 Add PIO20. Click Finish
Page 106 and 107: 22. Select System > Auto-Assign Bas
Page 108 and 109: Figure 7-38 SOPC Builder generation
Page 110 and 111: 33. Figure 7-42 show a blank Verilo
Page 112 and 113: Figure 7-43 Input verilog TextFigur
Page 114 and 115: 36. Compile the project, by selecti
Page 116 and 117: Figure 7-51 Blank Pins39. Input Loc
Page 118 and 119: Figure 7-54 Quartus II ProgrammerTh
Page 120 and 121: Figure 7-55 Nios II IDE New Project
Page 122 and 123: ● alt_sys_init.c: an initializati
Page 124 and 125: #include "system.h"#include "altera
Page 126 and 127: can write to the PIO data register,
Page 128 and 129: Figure 7-61 Configuring System Libr
Page 130 and 131: Figure 8-2 Pulse Width ModulationFi
Page 132 and 133: Table 8-1 DIP Switch SettingsDIP Sw
Page 134 and 135: Figure 8-5 ADC Reading hardware set
Page 136 and 137: • KEYThe KEY button is driven by
Page 138 and 139: Figure 8-11 4-wire SPI Timing Diagr
Page 140 and 141: • Input “1” to start Analog t
Page 142 and 143: In this demo, the accelerometer is
Page 146 and 147: Figure 9-3 Select Devices Page146
Page 148 and 149: Figure 9-5 Compression the sof file
Page 150 and 151: Figure 9-7 Erasing setting in Quart
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User Manual - Terasic

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