MEMORY DATABOOK - Al Kossow's Bitsavers

• DYNAMIC RAM· MSM41256AAS/RS .---------------Notes:12345678An initial pause of 100 JJ.s is required after power-up followed by any 8 RAS cycles(Example: RAS only) before proper device operation is achieved.The AC measurements assume tT = 5 nsVIH (Min.) and VIL (Max.) are reference levels for measuring of input signals. Also transitiontimes are measured between VIH and VIL.Assumes that tRCD ~ tRCD (Max.). If tRCD is greater than the maximum recommendedvalue shown in this table, tRAC will increase by the amount that tRCD exceeds the valueshown.Assumes that tRCD ~ tRCD (Max.).Measured with a load circuit equivalent to 2TTL loads and 100 pF.Operation within the tRCD (Max.) limit insures that tRAC (Max.) can be met. tRCD (Max.)is specified as a reference point only; if tRCD is greater than the specified tRCD (Max.)limit, then access time is controlled exclusively by tCAC.twcs and tCWD are not restrictive operating parameters. They are included in the datasheet as electrical charcteristics only; if twcs ~ twcs (min.), the cycle is an early writecycle and the data out pin will remain open circuit (high impedance) throughout theentire cycle; if tCWD ~ tCWD (min.), the cycle is read-write cycle and the data out willcontain data read from the selected cell; if neither of the above sets of conditions issatisfied the condition of the data out (at access time) is indeterminate.9 Page mode cycle.10 CAS before RAS Refresh Counter Test Cycle only.138