MEMORY DATABOOK - Al Kossow's Bitsavers

• DYNAMIC RAM· MSM411001 RS ••----------------AC CHARACTERISTICS (Continued)(Recommended operating conditions unless otherwise noted.)MSM411001 MSM411001Parameter Symbol Unit 10 12 NotesMin Max Min MaxNibble mode CAS precharge time tNCP ns 25 25 9Nibble mode read RAS hold time tNRRSH ns 40 40 9Nibble mode write RAS hold time tNWRSH ns 40 40 9Nibble mode CAS hold time referenced to RAS tRNH ns 20 20 9Refresh counter test cycle time tRTC ns 355 385 10Refresh counter test RAS pulse width tTRAS ns 255 10,000 275 10,000 10Refresh counter test CAS precharge time tCPT ns 50 60 10NOTES:1)2)3)4)5)6)7)8)An initial pause of 100 IJS is required after power-up followed by any 8 RAS cycles (Examples; RASonly) before proper device operation is achieved.AC measurements assume tT = 5 ns.VIH (Min.) and VIL (Max.) are reference levels for measuring timing of input signals. Also, transitiontimes are measured between VIH and VIL.Assumes that tRCO ~ tRCO (max.).If tRCO is greater than the maximum recommended value shown in this table, tRAC will increase bythe amount that tRCO exceeds the values shown.Assumes that tRCO ~ tRCO (max.)Measured with a load circuit equivale.nt to 2 TTL loads and 100 pF.Operation within the tRCO (max.) limit insures that tRAC (max.) can be met. tRCO (max.) is specifiedas a reference point only; if tRCO is greater than the specified tRCO (max.) limit, then accesstime is controlled exclusively by tCAC.twcs, tcwo and tRWO are not restrictive operating parameters. They are included in the data dheetas electrical characteristics only; if twcs2:twcs (min.). the cycle is an early write cycle and the dataout pin will remain open circuit (high impedance) throughout the entire cycle; if tcwo2:tcwo(min.),and tRWO 2:tRWO (min.) the cycle is read-write cycle and the data out will contain data read from theselected cell; if neither of the above sets of conditions is satisfied the condition of the data out (atacccess time) is indeterminate.9) Nibble mode cycle.10) CAS before RAS Refresh Counter Test Cycle only.208