MEMORY DATABOOK - Al Kossow's Bitsavers

• DYNAMIC RAM· MSM41256AAS/RS .1---------------FUNCTIONAL DESCRIPTIONSimple Timing Requirements:The MSM41256A has the circuit considerationsfor easy operational timing requirementsfor high speed access time operations. TheMSM41256A can operate under the condition oftRCD (max) = tCAC which provides an optimaltime space for address multiplexing. In addition,the MSM41 256A has the minimal hold time ofAddress (tCAH), WE (tWCH) and DIN (tDH). Andthe MSM41256A can commit better memorysystem through-put during operations in an inter~leaved system. Furthermore, Oki has madetiming requirements referenced to RAS nonrestrictiveand deleted from the data sheet,which includes tAR, tWCR, tDHR and tRWD·Therefore, the hold times of the Column AddressDIN and WE as well as tCWD (CAS to WE Delay)are not restricted by tRCD.Fast Read- While-Write Cycle:The MSM41 256A has the fast read whilewrite cycle which is achieved by excellent controlof the three-state output buffer in additionto the simplified timings described in the previoussection. The output buffer is controlled~the state of WE when CAS goes low. WhenWE is low during CAS transition to low, theMSM41256A goes to early write mode wherethe output becomes floating and common liDbus can be used on the system level. Whereas,when WE goes low after tCWD following CAStransition to low, the MSM41256A goes todelayed write mode where the Gutput containsthe data from the cell selected and the data fromDIN is written into the cell selected. Therefore,very fast read write cycle becomes available.Address Inputs:A total of eighteen binary input address bitsare required to decode any 1 of 262,144 storagecell location within the MSM41256A. Nine rowaddressbits are established on the input pins(Ao through AS> and latched with the Row AddressStrobe (RAS). Then nine column addressbits are established on the input pins andlatched with the Column Address Strobe (CAS).All input addresses must be stable on or beforethe falling edge of RAS. CAS is internally inhibited(or "gated") by RAS to permit triggering ofCAS as soon as the Row Address Hold Time(tRAH) specification has been satisfied and theaddress inputs have been changed from rowaddressesto column-addresses.Write Enable:The read or write mode is selected with theWE input. A logic "high" oli WE dictates readmode, logiC "low" dictates write mode. Data inputis disabled when read mode is selected.Data Input:Data is written into the MSM41256A during awrite or read-write cycle. The last falling edge ofWE or CAS is a strobe for the Data in (DIN)register. In a write cycle, if WE is brought "low"(write mode) before CAS, DIN is strobed by CAS,and the set-up and hold times are referenced toCAS.~ read-write cycle, WE will be delayeduntil CAS has made its negative transition. ThusDIN is strobed by WE, and set-up and hold timesare referenced to WE.Data Output:The output buffer is three-state TTL compatiblewith a fan-out of two standard TTL loads.Data out is the same polarity as data in. Theoutput is in a high impedance state until CAS isbrought "low". In a read cycle, or a read-writecycle, the output is valid after tRAC from transitionof RAS when tRCD (max) is satisfied, or aftertCAC from transition of CAS when the transitionoccurs after tRCD (max). Data remain valid untilCAS is returned to "high". In a write cycle, theidentical sequence occurs, but data is not valid.Page Mode:Page-mode operation permits strobing therow-address while maintaining RAS at a logiclow (0) throughout all successive memory operationsin which the row-address doesn't change.Thus the power dissipated by the negative goingedge of RAS is saved. Further, access and cycletimes are decreased because the time normallyrequired to strobe a new row-address is eliminated.144