MEMORY DATABOOK - Al Kossow's Bitsavers

_______________ • DYNAMIC RAM· MSM41257AAS/RS •FUNCTIONAL DESCRIPTIONSimple Timing Requirements:The MSM41257 A has the circuit considerationsfor easy operational timing requirementsfor high speed access time operations. TheMSM41257 A can operate under the condition oftRCD (max) = tCAC which provides an optimaltime space for address multiplexing. In addition,the MSM41257A has the minimal hold time ofAddress (tCAH), WE (tWCH) and DIN (tDH). Andthe MSM41257 A can commit better memorysystem through-put during operations in an interleavedsystem. Furthermore, Oki has madetiming requirements referenced to RAS nonrestrictiveand deleted from the data sheet,which includes tAR, tWCR, tDHR and tRWD·Therefore, the hold times of the Column AddressDIN and WE as well as tCWD (CAS to WE Delay)are not restricted by tRCD.Fast Read- While-Write Cycle:The MSM41 257 A has the fast read whilewrite cycle which is achieved by excellent controlof the three-state output buffer in additionto the Simplified timings described in the previoussection. The output buffer is controlledby the state of WE when CAS goes low. WhenWE is low during CAS transition to low, theMSM41257 A goes to early write mode wherethe output becomes floating and common liDbus can be used on the system level. Whereas,when WE goes low after tCWD following CAStransition to low, the MSM41257 A goes todelayed write mode where the output containsthe data from the cell selected and the data fromDIN is written into the cell selected. Therefore,very fast read write cycle .becomes available.Address Inputs:A total of eighteen binary input address bitsare required to decode any 1 of 262,144 storagecell location within the MSM41257 A. Nine rowaddressbits are established on the input pins(Ao through ABJ and latched with the Row AddressStrobe (RAS). Then nine column addressbits are established on the input pins andlatched with the Column Address Strobe (CAS).All input addresses must be stable on or beforethe falling edge of RAS. CAS is internally inhibited(or "gated") by RAS to permit triggering ofCAS as soon as the Row Address Hold Time(tRAH) specification has been satisfied and theaddress inputs have been changed from rowaddressesto column-addresses.Write Enable:The read or write mode is selected with theWE input. A logic "high" on WE dictates readmode, logic "low" dictates write mode. Data inputis disabled when read mode is selected.Data Input:Data is written into the MSM41 257 A during awrite or read-write cycle. The last falling edge ofWE or CAS is a strobe for the Data in (DIN)register. In a write cycle, if WE is brought "low"(write mode) before CAS, DIN is strobed by CAS,and the set-up and hold times are referenced toCAS. In a read-write cycle, WE will be delayeduntil CAS has made its negative transition. ThusDIN is strobed by WE, and set-up and hold timesare referenced to WE.Data Output:The output buffer is three-state TTL compatiblewith a fan-out of two standard TTL loads.Data out is the same polarity as data in. Theoutput is in a high impedance state until CAS isbrought "low". In a read cycle, or a read-writecycle, the output is valid after tRAC from transitionof RAS when tRCD (max) is satisfied, or aftertCAC from transition of CAS when the transitionoccurs after tRCD (max). Data remain valid untilCAS is returned to "high". In a write cycle, theidentical sequence occurs, but data is not valid.Nibble Mode:Nibble mode allows high speed serial read,write or read-modify-write access of 2, 3 or 4bits of data. The bits of data that may be accessedduring nibble mode are determined bythe 8 row addresses and the 8 column addresses.The 2 bits of addresses (CJ\a RAa) are usedto select 1 of the 4 nibble bits for initial access.After the first bit is accessed by normal mode,the remaining nibble bits may be accessed byCAS "high" then "low" while RAS remains "low".Toggling CAS causes RAa and CAa to be incrementedinternally while all other address bits areheld constant and makes the next nibble bitavailable for access. (See Table 1 )If more than 4 bits are accessed duringnibble mode, the address sequence will begin torepeat. If any bit is written during nibble mode,the new data will be read on any subsequentaccess. If the write operation may be executedagain on subsequent access, the new data willbe written into the selected cell location.In nibble mode, the three-state control ofDOUT Pin is determined by the first normal accesscycle.The data output is controlled by only WEstate referenced at CAS negative transition ofthe normal cycle (first Nibble bit). That is, whentwcs > twcs (min) is met, the data output willremain open circuit throughout the succeedingNibble cycle regardless of WE state. Whereas,when tCWD > tCWD (min) is met, the dataoutput will contain data from the cell selectedduring the succeeding nibble cycle regardless ofWE state. The write operation is done during theperiod where WE and CAS clocks are low.Therefore, write operation can be done bit by bitduring each nibble operation at any timing conditionsof WE (twcs and tCWD) at the normalcycle (first Nibble bit). 159