MEMORY DATABOOK - Al Kossow's Bitsavers

• DYNAMIC RAM· MSM3732AS/RS .11-----------------NOTES: 1)2)3)4)5)6)7)8)An initial pause of 1001's is required after power-up followed by any 8 RAS cycles (Examples; RASonly) before proper device operation is achieved.AC measurements assume tT = 5 ns.VIH (Min.) and VIL (Max.) are reference levels for measuring timing of input signals. Also, transitiontimes are measured between VI H and VI L.Assumes that tRCD < tRCD (max.).If tRCD is greater than the maximum recommended value shown in this table, tRAC will increase bythe amount that tRCDexceeds the value shown.Assumes that tRCD < tRCo (max.)Measured with a load circuit equivalent to 2 TTL loads and 100pF.Operation within the tRCD (max.) limit insures that tRAC (max.! can be met. tRCD (max.) is specifiedas a reference point only; if tRCD is greater than the specified tRCD (max.! limit, then accesstime is controlled exclusively by tCAC.twcs, tCWD and tRWD are not restrictive operating parameters. They are included in the data sheetas electrical characteristics only; if twcs ~ twcs (min.), the cycle is an early write cycle and the dataout pin will remain open circuit (high impedance) throughout the entire cycle; if tCWD ~ tCWD(min.! and tRWD > tRWD (min.) the cycle is read-write cycle and the data out will contain data readfrom the selected cell; if neither of the above sets of conditions is satisfied the condition of the dataout (at access time) is indeterminate.READ CYCLE TIMING~-------------------tRC------------------~~RASVIH -VIL -~------------tRAS------------~------,I ~-------tAR------~.~1 ~------~CASVIH -VIL --------'-''--------u.---.. 1-~-t-tCAS----~., r-'-+------,.DAddresses VIH-VIL -WEVIH-VIL -I----tCAC~----------tRAC----------~JtOFFDOUTVOH-VOL-OPENValid Data~ "H", "L" = Don't Care64