MEMORY DATABOOK - Al Kossow's Bitsavers

• DYNAMIC RAM· MSC2304YSS/KSS .1---------------Notes: 1234567An initial pause of 100 p's is required after power-up followed by any 8 RAS cycles(Example: RAS only) before proper device operation is achieved.AC measurements assume at tT = 5 nsVIH (Min.) and VIL (Max.) are reference levels for measuring timing of input signals. Alsotransition times are measured between VIH and VIL·Assumes that tRCD < tRCD (Max.)If tRCD is greater than the maximum recommended value shown in this table, tRAC willincrease by the amount that tRCD exceeds the values shown.Assumes that tRCD < tRCD (Max.).Measured with a load circuit equivalent to 2TTL loads and 100 pF.Operation within the tRCD (Max.) limit insures that tRAC (Max.) can be met. tRCD (Max.)is specified as a reference point only; if tRCD is greater than the specified tRCD (Max.)limit, then access time is controlled exclusively by tCAC.READ CYCLE TIMINGtRCRASVIH -VIL -CASVIH -VIL -VIH-Addresses VIL -DWEDOUTI tRcsHVIH-~rVIL-!--tCACtRACI-VOH-I OPENVOL-J tOFFValid Data~OOHOO, ooLoo = Don't Care250