MEMORY DATABOOK - Al Kossow's Bitsavers

• DYNAMIC RAM· MSM411 OOORS •• -----------------FUNCTIONAL DESCRIPTIONAddress Inputs:20 bits of binary address input are requiredto decode anyone of the 1,048,576 words by 1bit storage cell locations.10 row-address bits are set up on addressinput pins AO through A9 and latched onto thechip by the row address strobe (RAS). Then 10column-address bits are set up on pins AOthrough A9 and latched onto the chip by thecolumn address strobe (CAS).All addresses must be stable on or before thefalling edges of RAS. CAS is internally inhibited. (gated) by the RAS to permit triggering of CAS assoon as the Row Address Hold Time (tRAH)specification has been satisfied and the addressinputs have been changed from row-addressesto column-addresses.Therefore specifications permit columnaddresses to be input immediately after the rowaddress hold time (tRAH).Write Enable:The read mode or write mode is selected withthe WE input. The logic high of the WE inputselects the read mode and a logic low selectsthe write mode. The data input is disabled whenthe read mode is selected.Data Input:Data is written during a write or read-modifywrite cycle. Depending on the mode of operation,the falling edge of CAS or WE strobes data intothe on-chip data latches. In an early-write cycle,WE is brought low prior to CAS and the data isstrobed in by CAS with setup and hold timesreferenced to this signal. In a delayed write orread-modify-write cycle, CAS will already be low,thus the data will be strobed in by WE with setupand hold times referenced to this signal.Data Output:The three-state output buffer provides directTTL compatibility with a fan-out of two standardTTL loads. Data-out is the same polarity asdata-in. The output is in the high-impedance(floating) state until CAS is brought low. In a readcycle the output goes active after the accesstime interval tCAC that begins with the negativetransition of CAS as long as tRAC is satisfied.The output becomes valid after the access timehas elapsed and remains valid while CAS is low.CAS going high returns it to a high impedancestate. In an early-write cycle, the output isalways in the high impedance state.Page Mode:Page-mode operation permits strobing therow-address while maintaining RAS at a logiclow (0) throughout all successive memoryoperations in which the row-address doesn'tchange. Thus the power dissipated by thenegative going edge of RAS is saved. Further,access and cycle times are decreased becausethe time normally required to strobe a newrow-address is eliminated.RAS Only Refresh:Refresh of the dynamic memory cells is accomplishedby performing a memory cycle ateach of the 51 2 row-addresses (Ao to As) at leastevery 8 milliseconds. RAS only refresh avoidsany output during refresh because the outputbuffer is in the high impedance state unless CASis brought low. Strobing each of 512 (Ao to As)row-addresses with RAS will cause all bits ineach row to be refreshed. Further RAS-only refreshresults in a substantial reduction in .powerdissipation.CAS Before RAS Refresh:CAS before RAS refreshing offers analternate refresh method. If CAS is held on lowfor the specified period (tFCS) before RAS goesto low, on chip refresh control clock generatorsand the refresh address counter are enabled,and an internal refresh operation takes place.After the refresh operation is performed, therefresh address counter is automaticallyincremented in preparation for the next CASbefore RAS refresh operation.Hidden Refresh:Hidden refresh cycle may take place whilemaintaining latest valid data at the output byextending CAS active time. Hidden refreshmeans CAS before RAS refresh and the internalrefresh addresses from the counter are used torefresh addresses, because CAS is always lowwhen RAS goes to low in this mode.CAS Before RAS Refresh Counter Test Cycle:~ special timing sequence using CAS beforeRAS counter test cycle provides a convenientmethod of verifying the functionality of CASbefore RAS refresh activated circuitry. As shownin CAS before RAS Counter Test Cycle, if CASgoes to high and goes to low again while RAS isheld low, the read and write operation areenabled. This is shown in the CAS before RAScounter test cycle. A memory cell address,consisting of a row address (9 bits) and acolumn address (10 bits), to be acceded can bedefined as follows:• A ROW ADDRESS- Bits Ao through As are defined by therefresh counter.• A COLUMN ADDRESSAll the bits Ao through A9 are defined bylatching levels on Ao through A9 at thesecond falling edge of CAS.202