MEMORY DATABOOK - Al Kossow's Bitsavers

• APPLICATIONS •• ----------------------3. Data Retention Mode is cut until it reaches the power voltage for data retention(practically equivalent to the battery voltage, orThe RAM driver (peripheral circuit) is determinedaccording to conditions (1) and (3) required for dataretention. In Oki Electric CMOS RAMs, the powervoltage during data retention is kept at a minimum of2.0V. The CE (or CS) voltage at this time has to be keptat about Vcc -0.2V. And as was mentioned earlier, theCMOS Vee must drop smoothly when the system powerelse reduced by the diode voltage drop). And althoughCE traces the slope of CMOS Vcc reduction at this time,a smooth change in CE is also a necessary condition foractual circuits.(4) When switching to retention mode, or from retentionmode to operation mode, CE must exhibit asmooth change. If noise is generated in CE in this case,the data will be subject to rewriti ng.Cmos Vcc SV ± 10%Operation moder--- Data retention modeCE input VTH =Must be free of noiseVee - 2.0V (RAMP waveform)Other inputs VIL = . +(MIN) 'I ::.......::f,==========~t=======~::2.0V (MIN)I 'F Vcc- 0.2V0.8V(MG~X~-----Jt---~r: ______ I~ _____ O.SV(MAX)t = 0May be longerFig. 7(S) When switching to operation mode, commenceoperation after elapse of tRC (read cycle time) followingVcc reaching the operating power voltage range.Dataretention -tmodeIOperationmode.-/------+--...:.:.;.='--- CMOS Vee = SV ±10%:....t-------.-i, - --- - - ~- V I H = Vee - 2.0VCMOS Vee ' ' I 2.SV = 1/2Vcc (MIN)CE I ' ', j I I C"E VIL = 0.8V (MAX)GND-----~---- -1~-----~-----GNDMay be longertRC min.Fig. 8456