MEMORY DATABOOK - Al Kossow's Bitsavers

------------------. DYNAMIC RAM . MSM41464RS •Notes: 123456789An initial pause of 100 JJ.s is required after power-up followed by any 8 RAS cycles(Example: RAS only) before proper device operation is achieved.The AC characteristics assume at tT = 5 nsVIH (Min.) and VIL (Max.) are reference levels for measuring of input signals. Also transitiontimes are measured between VIH and VIL.Assumes that tRCD ~ tRCD (Max.) If tRCD > tRCD (Max.), tRAC will increase by {tRCD- tRCD (Max.)}.Assumes that tRCD ;;;, tRCD (Max.).Measured with a load circuit equivalent to 2TTL loads and 100 pF.Operation within the tRCD (Max.) limit insures that tRAC (Max.) can be met. tRCD (Max.)is specified as a reference point only; if tRCD is greater than the specified tRCD (Max.)limit, then access time is controlled exclusively by tCAC.Assumes that tRCD (Min.) = tRAH (Min.) + 2tT + tASC (Min.)twcs, tCWD and tRWD are not restrictive operating parameters. They are included inthe data sheet as electrical charcteristics only; if twcs > twcs (Min.), the cycle is anearly write cycle and the data in/data out pin will remain open circuit (high impedance)throughout the entire cycle; if tCWD ;;;, tCWD (Min.) and tRWD ;;;, tRWD (Min.) the cycleis read-write cycle and the data in/data out will contain data read from the selected cell;if neither of the above sets of conditions is satisfied the condition of the data out (ataccess time) is indeterminate.10 Either tRRH or tRCH must be satisfied for a read cycle.11 CAS before RAS refresh counter test cycle only.READ CYCLEtRASRAS V I H =-----i. 1------------'-"-"-".---------1 x.-------,L__ J----- tRsH------~---~~---_,r_ __ ~-------tCAs-----~CAS V IH -VIL-VILtcstRCAddresses V I HVlLVIH 77TT.n7TTTT.r.n777T---~-----------~-~~77TTTTTTTV I tCAC _____-II L ...LL..L.LLLI.".J..L.L.L£.L..l4T I------'~------tRAC ------~DATA VOH ______ _VOL - OPEN Valid DataV IHVIL LLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLL£~ __ -ZZLLLLLLLLLLLLLLLLLL~ "H", "L" = Don't Care169