MEMORY DATABOOK - Al Kossow's Bitsavers

-----------------. DYNAMIC RAM' MSM411 001 RS •Table 1 NIBBLE MODE ADDRESS SEQUENCE EXAMPLESEQUENCERAS/CAS {normal model 1 0NIBBLE BIT ROW ADDRESS COLUMN ADDRESSRA,toggle CAS (nibble model 2 1toggle CAS (nibble model 3 0toggle CAS (nibble model 4 1toggle CAS (nibble model 1 0CA,101010101 0 101010101 ----- input addresses101010101 0 101010101101010101 101010101 generated inter-101010101 101010101 nally101010101 0 101010101 1 sequence repeatsRAS only RefreshRefresh of the dynamic memory cells is accomplishedby perform ing a memory cycle at each of the 512 rowaddresses(Ao through Asl at least every 8 millisecond.RAS only refresh avoids any output during refreshbecause the buffer is in the high impedance state unlessCAS is brought "low". Strobing each of the 512 rowaddresses(Ao through Asl with RAS will cause all bitsin each row to be refreshed. Further RAS only refreshresults in a substantial reduction in power dissipation.CAS before RAS RefreshCAS before RAS refreshing available on theMSM411001 offers an alternate refresh method. IfCAS is held on "low" for the specified period (tFcslbefore RAS goes to "low", on chip refresh control clockgenerators and the refresh address counter are enabled,and an internal refresh operation takes place. After therefresh operation is performed, the refresh addresscounter is automatically incremented in preparationfor the next CAS before RAS refresh operation.Hidden RefreshHidden refresh cycle may takes place while maintaininglatest valid data at the output by extending CAS activetime from the previous memory read cycle. InMSM411001 hidden refresh means CAS before RASrefresh and the internal refresh addresses from thecounter are used to refresh addresses, because CAS isalways "low" when RAS goes to "low" in hiddenrefresh.CAS before RAS Refresh Counter TestCycleA speCialtiming sequence using CAS before RAScounter test cycle provides a convenient method of verifyingthe functionality of CAS before RAS refreshactivted circuitry.As shown in CAS before RAS Counter Test Cycle, ifCAS goes to "high" and goes to "low" again while RASis held "low", the read and write operations are enabled.A memory cell address (consisting of a row address (10bitsl and a column address (10 bitsll to be accessed canbe defined as follows:• A ROW ADDRESS -Bits Ao through As are definedby the refresh counter.The other bit A, is set "high" internally.• A COLUMN ADDRESS - All the bits Ao through A,are defined by latching levels on Ao throgh A, at thesecond falling edge of CAS.Suggested CAS before RAS Counter TestProcedureThe timing as shown in CAS before RAS Counter TestCycle is used for all the operations described as follows:(11 Initialize the internal refresh counter. For thisoperation, 8 cycles are required.(21 Write a test pattern of data "low" into memorycells at a single column address and 512 rowaddresses.(31 By using read-modify-write cycle, read the "low"written at the last operation (Step (211 and writea new data "high" in the same cycle. This cycle isrepeated 512 times, and data "high" are writteninto the 512 memory cells.(41 Read the data "high" written at the last operation(Step (311.(51 Complement the test pattern and repeat the steps(21, (31 and (41.215