MEMORY DATABOOK - Al Kossow's Bitsavers

• DYNAMIC RAM· MSC2301 YS9/KS9 .---------------HIDDEN REFRESH1-----Read Cycle----1--~-tAR--jIf-tRPAddressesDOUTrn!"H", "L" = Don't CareFUNCTIONAL DESCRIPTIONAddress Inputs:A total of sixteen binary input address bitsare required to decode any 1 of 65536 storagecell locations within the MSC2301. Eight rowaddressbits are established on the input pins(AD - A7) and latched with the Row AddressStrobe (RAS). The eight column-address bits areestablished on the input pins and latched withthe Column Address Strobe (CAS). All input addressesmust be stable on or before the fallingedge of RAS, CAS is internally inhibited (or"gated") by RAS to permit triggering of CAS assoon as the Row Address Hold Time (tRAH) specificationhas been satisfied and the addressinputs have been changed from row-addressesto column-addresses.Write Enable:The read mode or write mode is selected withthe WE input. A logic high (1) on WE dictatesread mode; logic low (0) dictates write mode.Data input is disabled when read mode isselected.Data Input:Data is written into the MSC2301 during awrite cycle. The last falling edge of WE or CAS isa strobe for the Data In (DIN) register. In a writecycle, if WE is brought low (write mode) beforeCAS, DIN is strobed by CAS, and the set-up andhold times are referenced to CAS.Data Output:The output buffer is three-state TTL compatiblewith a fan-out of two standard TTL loads.Data-out is the same polarity as data-in. Theoutput is in a high impedance state until CAS isbrought low. In a read cycle, the output is validafter tRAC from transition of RAS when tRCD(Max.) is satisfied, or after tCAC from transitionof CAS when the transition occurs after tRCD(Max.). Data remain valid until CAS is returned toa high level. In a write cycle the identical sequenceoccurs, but data is not valid.Page Mode:Page-mode operation permits strobing therow-address into the MSC2301 while maintainingRAS at a logic low (0) throughout all successivememory operations in which the rowaddressdoesn't change. Thus the pow~issipatedby the negative going edge of RAS issaved. Further, access and cycle times aredecreased because the time normally requiredto strobe a new row-address is eliminated.Refresh:Refresh of the dynamic memory cells is accomplishedby performing a memory cycle ateach of the 128 row-addresses (AD - As) atleast every two milliseconds. During refresh,either VIL or VIH is permitted for A7. RAS only refreshavoids any output during refresh becausethe output buffer is in the high impedance stateunless CAS is brought low. Strobing each of 128row-addresses with RAS will cause all bits in242