MEMORY DATABOOK - Al Kossow's Bitsavers

_______________.... DYNAMIC RAM· MSC2304YSS/KSS •HIDDEN REFRESHAddressesI tRCS IDOUT~ "H", "L" = Don't CareFUNCTIONAL DESCRIPTIONAddress Inputs:A total of eighteen binary input address bitsare required to decode any 1 of 262144 storagecell locations within the MSC2304. Nine rowaddressbits are established on the input pins(Ao - A8I and latched with the Row AddressStrobe (RAS). The Nine column-address bits areestablished on the input pins and latched withthe Column Address Strobe (CAS). All input addressesmust be stable on or before the fallingedge of RAg, CAS is internally inhibited (or"gated") by RAS to permit triggering of CAS assoon as the Row Address Hold Time (tRAH) specificationhas been satisfied and the addressinputs have been changed from row-addressesto column-addresses.Write Enable:The read mode or write mode is selected withthe WE input. A logic high (1) on WE dictatesread mode; logic low (0) dictates write mode.Data input is disabled when read mode isselected.Data Input:Data is written into the MSC2304 during awrite. The last falling edge of WE or CAS is astrobe for the Data In (DIN) register. In a writecycle, if WE is brought low (write mode) beforeCAS, DIN is strobed by CAS, and the set-up andhold times are referenced to CAS.Data Output:The output buffer is three-state TTL compatiblewith a fan-out of two standard TTL loads.Data-out is the same polarity as data-in. Theoutput is in a high impedance state until CAS isbrought low. In a read cycle, the output is validafter tRAC from transition of RAS when tRCD(Max.) is satisfied, or after tCAC from transitionof CAS when the transition occurs after tRCD(Max.). Data remain valid until CAS is returned toa high level. In a write cycle the identical sequenceoccurs, but data is not valid.Page Mo~e:Page-mode operation permits strobing therow-address into the MSC2304 whilemaintainingRAS at a logic low (0) throughout allsuccessive memory operations in which therow-address doesn't change. Thus the powerdissipated by the negative gOing edge of RAS issaved. Further, access and cycle times aredecreased because the time normally requiredto strobe a new row-address is eliminated.Refresh:Refresh of the dynamic memory cells is accomplishedby performing a memory cycle ateach of the 256 row-addresses (Ao - A7) atleast every four milliseconds. During refresh,either VIL or VIH is permitted for As. RAS only refreshavoids any output during refresh becausethe output buffer is in the high impedance stateunless CAS is brought low. Strobing each of 256row-addresses with RAS will cause all bits ineach row to be refreshed. Further RAS-only refreshresults in a substantial reduction in powerdissipation.Hidden Refresh:RAS ONLY REFRESH CYCLE may take placewhile maintaining valid output data. This featureis referred to as Hidden Refresh.Hidden Refresh is performed by holding CASas VIL from a previous memory read cycle.253