MEMORY DATABOOK - Al Kossow's Bitsavers

MOS MEMORY HANDLING PRECAUTIONS1. STATIC ELECTRICITY COUNTER·MEASURESSince voltage is generally controlled by means of thetransistor gate oxide film in MOS memories, the inputimpedance is high and the insulation tends to be destroyedmore readily by static electricity.Although Oki MOS memories incorporate built-inprotector circuits to protect all input terminals fromsuch destruction, it is not considered possible to givecomplete protection against heat destruction due toovercurrents and insulation film destruction due toirregular high voltages. It is, therefore, necessary toobserve the following precautionary measures.1) Under no circumstances must voltages or currentsin excess of the specified ratings be applied to anyinput terminal.2) Always use an electrically conductive mat or shippingtubes for storage and transporting purposes.3) Avoid wearing apparel made of synthetic fiberduring operations. The wearing of cottons which donot readily generate static electricity is desirable.Also avoid handling devices with bare hands. Ifhandling with bare hands cannot be avoided, makesure that the body is grounded, and that a 1MOresistor is always connected between the body andground in order to prevent the generation of staticelectricity.4) Maintaining the relative humidity in the operationroom at 50% helps to prevent static electricity.This should be remembered especially during dryseasons.5) When using a soldering iron, the iron should begrounded from the tip. And as far as possible, uselow power soldering irons (12 V or 24 V irons!.2; POWER SUPPLY AND INPUT SIGNALNOISE2.1 Power supply noise absorptionIn dynamic memories, the flow of power supplycurrent differs greatly between accessing and standbymodes.Although very little power is consumed by CMOSmemories during standby mode, considerable currentis drawn for charging and discharging (instantaneouscurrent requirements) during access mode. In order toabsorb the "spike noise" generated by these currentrequirements, the use of relatively large capacitancecapacitors (about one lO",F capacitor for every 8 to10 RAMs) is recommended along with good high fre·quency response capacitors of about O.l",F for eachmemory element. Power line wiring with as little lineimpedance as possible is also desirable.2.2 Input signal noise absorptionOvershooting and undershooting of the input signalshould be kept to a bare minimum. Undershooting inparticular can result in loss of cell data stability withinthe memory. For this reason,(1) Avoid excessive undershooting when using anaddress common bus for memory board RAMs andROMs.(2) Si nce noise can be generated very easily when usingdirect drive for applying memory board RAMaddresses from other driver boards, it is highlyrecommended that these addresses be first receivedby buffer.(3) Methods available for eliminating undershootinggenerated in the address line includea) Clamping of the undershooting by including adiode.b) Connect 10-200 in series with driver outputs.c) Smooth the rising edge and fall ing edge waveforms.3. CMOS MEMORY OPERATINGPRECAUTIONS3.1 Latch-UpIf the CMOS memory input signal level exceeds theVcc power line voltage by +0.3 V, or drops below theground potential by -0.3 V, the latch-up mechanismmay be activated. And once this latch·up mode hasbeen activated, the memory power has to be switchedoff before normal operating mode can be restored.Destruction of the memory element is also possible ifthe power is not switched off.Although Oki CMOS memories have been designedto counter these tendencies, it is still recommended thatinput signal overshooting and undershooting by avoided.3.2 Battery Back-UpTake special note of the following 4 pOints whendesigning battery back-up systems.(1) Do not permit the input signal H level to exceedVee +0.3 V when the memory Vcc power is dropped.To achieve this, it is recommended that a CMOSdriver using a Vcc power common with the CMOSmemory, or an open collector buffer or open drainbuffer pulled-up by a Vcc power common with the·CMOS memory be used for driving purposes.(2) Set the chip select input signal CE to the same Hlevel as the CMOS memory Vcc power line. And inorder to minimize memory power consumption, setthe write enable input WE level, the address inputarid the data input to either ground level or to thesame H level as the CMOS memory Vcc power line.(3) Make sure that the CMOS memory Vcc power line isincreased without "ringing" or temporary breakswhen restoring the battery back-up mode.(4) When using synchronous type CMOS memories(MSM5115, MSM51 04), make sure that accessingoccurs after elapse of the chip enable off time (tcc)prescribed in the catalog after the Vcc power linehas reached the guaranteed operating voltage range.For further details, refer to "CMOS Memory BatteryBack·up" at the end of this manual.35