MEMORY DATABOOK - Al Kossow's Bitsavers

• DYNAMIC RAM' MSM411 001 RS •• ----------------~DESCRIPTIONSimple nming RequirementThe MSM411001 has the circuit considerations for easyoperational timing requirements for high speed accesstime operations. The MSM411001 can operate underthe condition of tRCD (max) = tCAC which provides anoptimal time space for address mUltiplexing. In addition,the MSM411001 has the minimal hold times ofAddress (tCAH), WE (tWCH) and DIN (tDHl. Andthe MSM411001 can commit better memory systemthrough-put during operations in an inter-leaved system.Fast Read- While-Write cycleThe MSM411001 has the fast read while write cyclewhich is achieved by excellent control of the three-stateoutput buffer in addition to the simplified timingsdescribed in the previous section. The output buffer iscontrolled by the state of WE when CAS' goes low.When WF. is low during CAS transition to low, theMSM411001 goes to early write mode where the outputbecomes floating and common 1/0 bus can be used onthe system level. Whereas, when WE goes low aftertCWDfoliowing CAS transition to low, the MSM411001goes to delayed write mode where the output containsthe data from the cell selected and the data from 0 I Nis written into the cell selected. Therefore, very fastread write cycle becomes available.Address InputsA total of twenty binary input address bits are requiredto decode any 1 of 1048576 storage cell locations withinthe MSM411 001. Nine row-address bits are establishedon the input pins (Ao through A,) and latched withthe Row Address Strobe (RAS). Then ten columnaddress bits are established on the input pins and latchedwith the Column Address Strobe (CAS). All inputaddresses must be stable on or before the falling edge ofRAS. CAS is internally inhibited (or "gated") by RASto permit triggering of CAS as soon as the Row AddressHold Time (tRAH) specification has been satisfiedand the address inputs have been changed from rowaddressesto column-addresses.Write EnableThe read or write mode is selected with the WE input.A logic "high" on WE dictates read mode, logic "low"dictates write mode. Data input is disabled when readmode is selected.Data InputData is written into the MSM411001 during a write orread-write cycle. The last falling edge of WE or CAS isa strobe for the Data in (DIN) register. In a write cycle,if WE is brought "low" (write mode) before CAS, DINis strobed by CAS, and the set-up and hold times arereferenced to CAS. In a read-write cycle, WE will bedelayed until CAS has made its negative transition.Thus DIN is strobed by WE, and set-up and hold timesare referenced to WE.Data OutputThe output buffer is three-state TTL compatible with afan-out of two standard TTL loads. Data out is thesame polarity as data in. The output is in a high impedancestate until CAS is brought "low". In a read cycle,or a read-write cycle, the output is valid after tRACfrom transistion of RAS when tRCD(max) is satisfied,or after tCAC from' transition of CAS when the transitionoccurs after tRCD (maxl. Data remain valid untilCAS is returned to "high". In a write cycle, the identicalsequence occurs, but data is not valid.Nibble ModeNibble mode allows high speed serial read, write or readmodify-writeaccess of 2, 3 or 4 bits of data. The bitsof data that may be accessed during nibble mode aredetermined by the 9 row addresses and the 9 columnaddresses. The 2 bits of addresses (CA, RA,) are usedto select 1 of the 4 nibble bits for initial access. Afterthe first bit is accessed by normal mode, the remainingnibble bits may be accessed by CAS "high" then "low"while RAS remains "low". Toggling CAS causes RA,and CA, to be incremented internally while all otheraddress bits are held constant and makes the next nibblebit available for access. (See Table 1)If more than 4 bits are accessed during nibble mode, theaddress sequence will begin to repeat. If any bit iswritten during nibble mode, the new data will be readon any subsequent access. If the write operation maybe executed again on subsequent access, the new datawill be written into the selected cell location.In nibble mode, the three-state control of DOUT Pin isdetermined by the first normal access cycle.The data output is controlled by only WE state referencedat CAS negative transition of the normal cycle(first Nibble bitl. That is, when twcs > twcs (min) ismet, the data output will remain open ci rcuit throughoutthe succeeding Nibble cycle regardless of WE state.Whereas, when tCWD > tCWD (min) is met, the dataoutput will contain data from the cell selected duringthe succeeding nibble cycle regardless of WE state. Thewrite operation is done during the period where WE andCAS clocks are low. Therefore, write operation can bedone bit by bit during each nibble operation at anytiming conditions of WE (twcs and tCWD) at thenormal cycle (first Nibble bit).214