MEMORY DATABOOK - Al Kossow's Bitsavers

• DYNAMIC RAM· MSM414256RS •• -----------------CAS Before RAS Refresh Counter Test Cycle:A special timing sequence using CAS beforeRAS counter test cycle provides a convenientmethod of verifying the functionality of CAS"before RAS refresh activated circuitry. As shownin CAS before "RAS Counter Test Cycle, if CASgoes to high and goes to low again while 'RAS isheld low, the read and write operation areenabled. This is shown in the CAS before RAScounter test cycle. A memory cell address,consisting of a row address (9 bits) and acolumn address (9 bits), to be acceded can bedefined as follows:• A ROW ADDRESS- Bits AD through As are defined by therefresh counter.• A COLUMN ADDRESSAll the bits AD through As are defined bylatching levels on AD through As at thesecond falling edge of CAS".Suggested CAS before RAS Counter TestProcedure:The timing, as shown in CAS before RASCounter Test Cycle, is used for all the operationsdescribed as follows:(1) Initialize the internal refresh counter. Forthis operaton, 8 cycles are required.(2) Write a test pattern of lows into memorycells at a single column address and 512row addresses.(3) By using read-modify-write cycle, read thelow written at the last operation (Step (2))and write a new high in the same cycle. Thiscycle is repeated 512 times, and highs arewritten into the 512 memory cells.(4) Read the high written at the last operation(Step (3».(5) Complement the test pattern and repeat thesteps (2), (3) and (4).190