MEMORY DATABOOK - Al Kossow's Bitsavers

64K BIT DYNAMIC RAM APPLICATION NOTES1. MEMORY DRIVERThere are problems in driving MOS ICs by a TTL driver:increase of driver delay time due to capacitive load andringing waveform at the falling edge.An example of the increase of delay time due to capacitiveload is shown in the following figure.The number of load memory elements must be takeninto consideration when designing the timing.In case of LS type2018..s 16..E 14i=i;" 12~ 108642oPROPAGATION DELAY TIMEvsLOAD CAPACITANCEVCC= 5VRL = 25nTa = 25°CV/' ~ VyV ---/V Vo 10 20 30 40 50 60 70 80 90 100CL - Load Capacitance - pFelf the number of load memory el&ments is 20 - 40(150 - 300pF} on a two layer board, an undershootof -2 to -3V (peak voltage} occurs. Therefore, measuresagainst ringing must be taken as described in thefollowing.e Measures against ringing(1) No consideration is required for the rising edgesince there is a margin.(2} Since ringing may be considered as a reflectiondue to mismatching between the driver outputimpedance and signal line impedance, it can beprevented by line matching (termination}.For memory arrays, however, termination withpull up or bleeder resistance is not effective.Instead, series resistance (damping resistance} issuitable for memory arrays.(3} The optimal value of series resistance differsdepending upon the speed, pattern status, anddriver. Experience will help in determining theoptimal series resistance .As a general ru Ie, a resistance of 10 - 100n issuitable.However the speed will be lowered if the resistanceis too large. An example is shown inattached drawing 3.(4} Make the signal lines as short as possible. Multilayerboard design is effective in reducing theundershoot (as the signal line impedance islowered}.In case of L type'5112, '5113, '5114AVERAGE PROPAGATION DELAY TIMECLOCK TO OUTPUTvsLOAD CAPACITANCE16i;"a;14Cc:o12.~ 10§r:t..~~I...J::t:~+N::t:...J~8642o oVCC= 3VRL = 280nTa = 25°C/' V.....- .....-V V25 50 75 100 125 150 175200CL - Load Capacitance - pFill445