PCT/2001/45 - World Intellectual Property Organization

45/2001
20344 PCT Gazette - Section I - Gazette du PCT 8 Nov/nov 2001
(81) KR US.
(84) EP (AT BE CH CY DE DK ES FI FR GB GR
IE IT LU MC NL PT SE TR).
(51) 7 H01L 21/68, 21/66, H05B 3/10, 3/20, 3/68,
3/06, 3/16
(11) WO 01/84623
(21) PCT/JP01/03680
(13) A1
(22) 27 Apr/avr 2001 (27.04.2001)
(25) ja (26) ja
(30) 2000-132123 1 May/mai 2000
(01.05.2000)
JP
(30) 2000-202509 4 Jul/juil 2000
(04.07.2000)
JP
(30) 2001-48977 23 Feb/fév 2001
(23.02.2001)
JP
(43) 8 Nov/nov 2001 (08.11.2001)
(54) HOT PLATE UNIT AND SEMICON-
DUCTOR MANUFACTURING AND
INSPECTING DEVICE
UNITE DE PLAQUE CHAUFFANTE
ET DISPOSITIF DE PRODUCTION ET
DE CONTROLE DE SEMI-CONDUC-
TEURS
(71) IBIDEN CO., LTD. [JP/JP]; 1, Kandacho
2-chome, Ogaki-shi, Gifu 503-0917 (JP).
(for all designated States except / pour tous
les États désignés sauf US)
(72, 75) HIRAMATSU, Yasuji [JP/JP]; c/o
IBIDEN CO., LTD., 1-1, Kitagata, Ibigawacho,
Ibi-gun, Gifu 501-0695 (JP). ITO,
Yasutaka [JP/JP]; c/o IBIDEN CO., LTD.,
1-1, Kitagata, Ibigawacho, Ibi-gun, Gifu
501-0695 (JP).
(74) YASUTOMI, Yasuo et al. / etc.; Chuo
BLDG., 4-20, Nishinakajima 5-chome, Yodogawa-ku,
Osaka-shi, Osaka 532-0011 (JP).
(81) US.
(84) EP (AT BE CH CY DE DK ES FI FR GB GR
IE IT LU MC NL PT SE TR).
(51) 7 H01L 21/68
(11) WO 01/84624 (13) A2
(21) PCT/US01/13405
(22) 25 Apr/avr 2001 (25.04.2001)
(25) en (26) en
(30) 09/561,585 28 Apr/avr 2000 US
(28.04.2000)
(43) 8 Nov/nov 2001 (08.11.2001)
(54) SEMICONDUCTOR LIFT PIN FOR
DECHUCKING SUBSTRATES
BROCHE DE RELEVAGE DE SEMI-
CONDUCTEUR POUR LE DESSER-
RAGE DES SUBSTRATS
(71) APPLIED MATERIALS, INC. [US/US];
P.O. Box 450 A, Santa Clara, CA 95052 (US).
(72) LOEWENHARDT, Peter, K.; 1862 Rosswood
Drive, San Jose, CA 95124 (US).
HANAWA, Hiroji; 696 Spruce Drive, Sunnyvale,
CA 94086 (US). GRISTI, Raymond;
4110 Wingham Place, San Jose, CA 95135
(US). YIN, Gerald, Zheyao; 5511 Country
Club Drive, San Jose, CA 95138 (US). YE,
Yan; 13271 Via Arriba Drive, Saratoga, CA
95070 (US).
(74) BERNADICOU, Michael, A. et al. / etc.;
Blakely, Sokoloff, Taylor & Zafman LLP, 7th
Floor, 12400 Wilshire Boulevard, Los Angeles,
CA 90025 (US).
(81) JP.
(51) 7 H01L 21/762, 21/8247
(11) WO 01/84625 (13) A1
(21) PCT/US01/10922
(22) 3 Apr/avr 2001 (03.04.2001)
(25) en (26) en
(30) 09/563,179 2 May/mai 2000 US
(02.05.2000)
(43) 8 Nov/nov 2001 (08.11.2001)
(54) FLASH MEMORY ARRAY AND A
METHOD AND SYSTEM OF FABRI-
CATION THEREOF
TABLEAU DE MEMOIRE FLASH, PRO-
CEDE ET SYSTEME DE FABRICATION
CORRESPONDANTS
(71) ADVANCED MICRO DEVICES, INC.
[US/US]; One AMD Place, Mail Stop 68,
Sunnyvale, CA 94088-3453 (US).
(72) CHAN, Maria, C.; 3427 San Saba Drive,
San Jose, CA 95148 (US). FANG, Hao; 7719
Carriage Circle, Cupertino, CA 95014 (US).
CHANG, Mark, S.; 1881 Farndon Avenue,
Los Altos, CA 94024 (US). TEMPLETON,
Michael; 80 Palmer Lane, Atherton, CA
94027 (US).
(74) RODDY, Richard, J.; Advanced Micro Devices,
Inc., Mail Stop 68, One AMD Place,
Sunnyvale, CA 94088-3453 (US).
(81) AE AG AL AM AT AU AZ BA BB BG BR
BY BZ CA CH CN CO CR CU CZ DE DK
DM DZ EE ES FI GB GD GE GH GM HR
HU ID IL IN IS JP KE KG KP KR KZ LC
LK LR LS LT LU LV MA MD MG MK MN
MW MX MZ NO NZ PL PT RO RU SD SE
SG SI SK SL TJ TM TR TT TZ UA UG UZ
VN YU ZA ZW.
(84) AP (GH GM KE LS MW MZ SD SL SZ TZ
UG ZW); EA (AM AZ BY KG KZ MD RU
TJ TM); EP (AT BE CH CY DE DK ES FI
FR GB GR IE IT LU MC NL PT SE TR); OA
(BF BJ CF CG CI CM GA GN GW ML MR
NE SN TD TG).
Published / Publiée :(c)
(51) 7 H01L 21/768
(11) WO 01/84626
(21) PCT/JP01/03618
(13) A1
(22) 26 Apr/avr 2001 (26.04.2001)
(25) en (26) en
(30) 2000-131378 28 Apr/avr 2000
(28.04.2000)
JP
(43) 8 Nov/nov 2001 (08.11.2001)
(54) SEMICONDUCTOR DEVICE HAVING
A LOW DIELECTRIC FILM AND FAB-
RICATION PROCESS THEREOF
DISPOSITIF SEMI-CONDUCTEUR
POURVU D’UN FILM FAIBLEMENT
DIELECTRIQUE ET PROCEDE DE FA-
BRICATION CORRESPONDANT
(71) TOKYO ELECTRON LIMITED [JP/JP];
3-6, Akasaka 5-Chome, Minato-Ku, Tokyo
107-8481 (JP).
(for all designated States except / pour tous
les États désignés sauf US)
(72, 75) MAEKAWA, Kaoru [JP/JP]; c/o
TOKYO ELECTRON LIMITED, 650,
Mitsuzawa, Hosaka-Cho, Nirasaki-Shi,
Yamanashi 407-0192 (JP). SUGIURA,
Masahito [JP/JP]; c/o TOKYO ELECTRON
LIMITED, 650, Mitsuzawa, Hosaka-Cho,
Nirasaki-Shi, Yamanashi 407-0192 (JP).
(74) ITOH, Tadahiko; 32nd Floor, Yebisu Garden
Place Tower, 20-3, Ebisu 4-chome,
Shibuya-ku, Tokyo 150-6032 (JP).
(81) CN JP KR US.
(84) EP (AT BE CH CY DE DK ES FI FR GB GR
IE IT LU MC NL PT SE TR).
Published / Publiée :(a)
(51) 7 H01L 21/768, 23/532
(11) WO 01/84627
(21) PCT/US01/14225
(13) A2
(22) 2 May/mai 2001 (02.05.2001)
(25) en (26) en
(30) 09/563,740 3 May/mai 2000
(03.05.2000)
US
(43) 8 Nov/nov 2001 (08.11.2001)
(54) ELECTRONIC DEVICES WITH DIFFU-
SION BARRIER AND PROCESS FOR
MAKING SAME
DISPOSITIFS ELECTRONIQUES COM-
PRENANT UNE BARRIERE DE DIFFU-
SION ET PROCEDE DE FABRICATION
DE CETTE DERNIERE
(71) THE GOVERNMENT OF THE UNITED
STATES OF AMERICA, represented
by THE SECRETARY OF THE NAVY
[US/US]; Naval Surface Warfare Center,
Dahlgren Division,
(US).
Dahlgren, VA 22448
(72) CHU, Tak, Kin; 5838 Conway Road,
Bethesda, MD 20817 (US). SANTIAGO,
Francisco; 5308 Cedar Ridge Drive, Fredericksburg,
VA 22407 (US). BOULAIS,
Kevin, A.; 1315 Wilson Road, Waldorf, MD
20602 (US).
(74) BECHTEL, James, B.; NSWC- Dahlgren
Division, Office of Patent Counsel, Code
CD222, Building 183, Room 015, 17320
Dahlgren Road, Dahlgren, VA 22448-5100
(US).
(84) EP (AT BE CH CY DE DK ES FI FR GB GR
IE IT LU MC NL PT SE TR).
(51) 7 H01L 21/8238, 21/336, 21/311
(11) WO 01/84628
(21) PCT/CA01/00639
(13) A1
(22) 3 May/mai 2001 (03.05.2001)
(25) en (26) en
(30) 0010650.0 4 May/mai 2000
(04.05.2000)
GB
(43) 8 Nov/nov 2001 (08.11.2001)
(54) METHOD OF FORMING SPACERS IN
CMOS DEVICES
REALISATION DE CALES D’ECARTE-
MENT DANS DES CIRCUITS CMOS
(71) MITEL CORPORATION [CA/CA]; 400
March Road, Kanata, Ontario K2K 3H4
(CA).
(72) ROY, Marc; 85 Levis Street, Granby, Quebec
J2N 2G2 (CA). DAIGLE, Manon; 11
Principal Ouest, Farnham, Quebec J2N 1K4