Prospects of Colloidal Nanocrystals for Electronic - Computer Science

Colloidal Nanocrystals in Electronic Applications Chemical Reviews, 2010, Vol. 110, No. 1 441
conventional flash memory is extremely prone to failure of
insulation; one weak spot in the tunneling oxide is sufficient
to create a fatal discharge path (Figure 56d). A promising
way to alleviate this problem, while still preserving the
fundamental operation principles of the flash memory, is to
store charge not on the continuous poly silicon FG, but on
a layer of discrete, mutually isolated NCs (Figure 56b). Each
NC will store only few electrons; collectively, the charges
stored on NCs can control the threshold voltage of the FET.
The concept of distributed charge storage is more faulttolerant
because minor damages in the tunnel oxide layer
are not detrimental for memory operation (Figure 56e).
Thinner tunneling oxide can be used to achieve lower
operating voltages and/or increase the operating speed.
The properties of a thin SiO2 dielectric layer can be
seriously degraded under continuous memory programming
(write/erase), and this severely decreases the data retention
time of conventional and NC-based flash memory devices.
Stability increases with increasing oxide thickness; however,
thicker oxide layer reduces the tunneling current through
dielectric layer, requires higher operating voltages for write/
erase, and puts restrictions on down-scaling dimensions of
the nodes. For most flash memories, the retention time and
operating speed are in inverse proportion to each other.
Several approaches have been studied to achieve the fast
programming speed (write/erase) and the long retention time
of memory simultaneously. 583-585 Recently, researchers have
focused on improving data retention time without decreasing
the programing speed at low voltages. 586-588 For this purpose,
it was proposed to replace the conventional SiO2 dielectric
layer with a high-k gate dielectric for the control and tunnel
oxide layers. High-k dielectric materials with lower conduction
band offsets with Si provide lower tunneling barriers at
the dielectric channel.
The idea of NC-based flash memory has been proposed
in 1996 by IBM. 571,582 Since then, different metal and
semiconductor NCs have been tested as FGs. 589-592 The
integration of 5 nm Si NCs into the gate oxide strongly
affects the transfer characteristics of the MOSFET as shown
in Figure 57. 593 In the control device where no FG is
embedded into gate insulator, the drain current (ID) versus
gate voltage (VG) scans show no hysteretic behavior; ID has
same magnitude when VG is scanned from -4 to4Vand
when VG is scanned from 4 to -4 V (Figure 57, dashed
curve). However, huge hysteresis of transistor transfer
characteristics is observed when small Si NCs are integrated
into the gate oxide. For example, the difference in ID
measured during forward and backward gate scans exceeds
10 6 at VG ) 0 V (Figure 57, solid curve). 593 Such behavior
is fully consistent with flash memory operation principles
described above; charging of NCs shifts the FET threshold
voltage. The performance of NC flash memories depends
strongly on the accurate control of NC size, density, and
their uniform distribution in a thin layer of oxide. 590,592,594,595
Si and Ge Nanocrystal-Based Flash Memory Devices.
Si NCs-based FG memory is seriously considered among
the candidates for the next generation of nonvolatile memory
devices. 370,571-573,584,596-604 Tiwari et al. reported the first Si
NC-based FG memory device embedded in a SiO2 layer. 571
The device operation is based on direct tunneling and storage
of electrons in the NCs (also called nodes). Capacitance and
size of the NCs limit the number of stored charges per node.
Electron-injection occurs through direct tunneling from an
inversion layer when positive (with respect to the source and
Figure 57. Transfer characteristics (ID vs VG scan) of a nanocrystalbased
flash memory device consisting of FET and the floating gate
made of ∼5 nm Si nanocrystals separated from the transistor
channel by a thin 9 nm layer of HfO2 tunnel oxide and from the
control gate by a thicker layer (20 nm) of SiO2 control oxide. The
presence of Si nanocrystals introduces hysteretic behavior of FET
transter characteristics (solid line). The control experiment with
same thicknesses of HfO2 and SiO2 layers but without Si nanocrystals
shows nearly ideal transistor behavior with no hysteresis
(dashed line). Reprinted with permission from ref 593. Copyright
2006 American Institute of Physics.
drain electrodes) gate voltage is applied (+VG). Such devices
demonstrate high speed operation (less than 100s of nanosecond
per write-erase cycle), small dimensions, and long
operation times (excess of 10 9 cycles). 571 The performance
of Si-based memories depends on the accurate control of
NC size, density, and arrangement in the thin oxide.
Punchaipetch et al. studied the effect of tunnel layer
thickness on the memory performance (write/erase) and data
retention of Si NC-based floating gate devices. 605 The 10
nm SiO2 tunnel oxide showed the most stable performance
as compared to the 3 and 5 nm oxide layer. Degradation of
threshold voltage was not observed even after 10 8 operating
cycles. Lu et al. reported the effect of NC density on the
operation of the floating gate memory. 606 It was shown
that the operating speed can be further increased by increasing
the density of NCs in the FG layer. As mentioned above,
the retention time is inversely correlated to the thickness of
the tunnel oxide layer.
King et al. reported the gemanium NC memory devices
that could operate at low voltages and high speeds superior
to Si-based memory devices. 579 The device consisted of
MOSFET with Ge NC FGs embedded within the gate
dielectric. Lu et al. also reported the memory devices with
Ge NCs embedded in LaAlO3 (LAO) high-k dielectric. 607
This device showed a significant memory effect with a very
high density of stored charge up to 2 × 10 13 /cm 2 . A
maximum shift in the threshold voltage of 3.2 V was
achieved for the trilayer structure of LAO(8 nm)/Ge_NCs/
LAO(3 nm)/Si. Ge NC FGs showed excellent charge
retention time, whereas the decay in memory capacitance
after 10 4 s of stress under a flat band voltage was only 8%.
Kim et al. compared memory characteristics of SiGe NCs
embedded in HfO2 or SiO2 dielectric layers. 558 Reported
results indicated that the HfO2 tunneling oxide with SiGe
NCs shows a faster charge carrier trapping and detrapping