TH ESE Mohamed H edi TOUATI TEST ET ... - Laboratoire TIMA

| Bibliographie |
[HRA88] A. Hassan, J. Rajski et V. K. Agrawal, "Testing and Diagnosis of Interconnects
using Boundary Scan Architecture", International Test Conference, 1988,
pp. 254-265.
[HaW92] J. K Hagge and R. J. Wagner, "High-Yield Assembly of Multi-Chip Modules
through Known-Good IDs and Eective Test Strategies", Proceedings of the
IEEE, Vol. 80, N. 12, December 1992, pp. 1965-1994.
[Han89] P. Hansen, "Testing Conventional Logic and Memory Clusters using Boundary
Scan Devices as Virtual ATE Channels", International Test Conference, 1989,
pp. 166-173.
[IEEE90] IEEE Standard 1149.1-1990, "IEEE Standard Acess Port and Boundary
Scan Architecture", IEEE Standards Board, 345 East 47th Street, New York,
NY 10017-2394, USA, 1990.
[JaY89] N. Jawarla et C. Yau, "A New Framework for Analyzing Test Generation and
Diagnosis Algorithms for Wiring Interconnects", International Test Conference,
1989, pp. 63-70.
[JTB91] R. W. Johnson, R. K. F. Teng and J.W. Balde. Ed. "MultiChip Modules".
IEEE Press Selected Reprint Series. 1991.
[Kau74] W. Kautz, "Testing for faults in Wiring Networks", IEEE Transactions on
Computers, Vol. C-23, N o 4, April 1974, pp. 358-363.
[KlW87] J. De. Dekleer and B.C Williams. "Diagnosing multiple faults", Articial
intelligence, Vol 32, pp. 97-130, 1987.
[Kos91] B. Kosko "Neural Networks and Fuzzy Systems", Prentice Hall, 1991.
[Kui93] B. Kuipers, "Reasoning with qualitative models", Articial Intelligence, vol
59, 1993.
[Lan91] D. Lang, "Cost Eectiveness of nCHIP's MCM Technology", MultiChip Module
Workshop, Santa Cruz, March 1991, pp. 16-23.
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