TH ESE Mohamed H edi TOUATI TEST ET ... - Laboratoire TIMA

Abstract
Today's Integrated Circuits are made of millions of transistors, Printed Circuit
Boards (PCBs) can have up to ten layers allowing integration of a large number of
components and new packaging technologies have appeared, such as 3D packaging or
Multi-Chip Modules (MCMs). According to this reality, Test and Diagnostic tasks
have become essential for prototype validation and maintenance.
The IEEE 1149.1 Boundary Scan Standard (BS) allows to cope with state-of-the
art packaging and wiring technologies. Although researchevolves from the assumption
of full BS availability, industry must face a market which has just started integrating
this standard. So, systems will still contain BS parts and non BS clusters in the near
future.
This thesis aims at nding a global approach for the test and diagnosis of such
heterogeneous systems.
We propose a methodology which unies the test and diagnosis of components
and their interconnects. It is based on a scheduling approach to test simultaneously
both BS components and non BS clusters, as well as interconnects. Logical stuck-at
faults, as well as short and open faults are addressed.
Diagnosis is achieved thanks to a novel approach combining structural description
and qualitative reasoning to generate fault candidates. A fuzzy logic-based strategy
for best test point nding is used to enhance the diagnosis accuracy and eciency.
This methodology, which can be applied to both MCMs and PCBs, has been
implemented in a software, nicely interfaced to commercial ATPGs. Obtained experimental
results validate this methodology.
Keywords: ATPGs, Boundary Scan, Test, Diagnostis, PCBs, MCMs.
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