The IBM eServer BladeCenter JS20 - IBM Redbooks

These components all interact with storage as illustrated in Figure 2-8.
Instructions
from Storage
Fixed-Point
Instructions
Fixed-Point
Processing
(FXU)
Figure 2-8 PowerPC logical processing model
A PowerPC Architecture groups the instructions that an application program uses
on a PowerPC processor along the same lines into:
► Fixed-point instructions
► Floating-point instructions
► Branch instructions
All instructions in PowerPC Architecture are four bytes (one word) in size and are
aligned on word boundaries. This simplifies the decoding of instructions and is
characteristic of a RISC architecture.
The fixed-point instructions operate on a set of 32 general purpose registers
(GPRs), that are each 8 bytes (64 bits) in size on 64-bit PowerPC Architecture
processors. There is also a fixed-point exception register (XER). In 32-bit mode,
only the lower 32 bits of the GPRs are considered significant, and the double
word load and store instructions are not available.
The floating-point instructions operate on a set of 32 floating-point registers
(FPRs), that are each 8 bytes (64 bits) in size. There is also a floating-point
status and control register (FPSCR). The floating point capabilities are the same
in both 32-bit and 64-bit mode. The large number of GPRs and FPRs is also
typical of a RISC architecture.
34 The IBM Eserver BladeCenter JS20
Branch
Processing
(BPU)
Data to/from
Storage
Storage
Floating-Point
Instructions
Floating-
Point
Processing
(FPU)