The IBM eServer BladeCenter JS20 - IBM Redbooks

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PowerPC 970 and PowerPC 970FX processors These processors were first used by IBM in the BladeCenter JS20 that is the subject of this book. We explore these processors in more detail in 2.3, “PowerPC 970 and PowerPC 970FX Microprocessors” on page 29. POWER5 processor IBM recently introduced the POWER5 processor in the IBM Eserver i5 and p5 families of servers. The POWER5 processor represents an evolution of the POWER4 processor. Like the POWER4, the POWER5 processor implements two processor cores on a single chip with a shared level-2 cache. The major innovation in the POWER5 processor is the introduction of symmetrical multi-threading (SMT) capabilities. SMT enables two threads of execution (contexts) to execute simultaneously on the same processor core. This can improve the performance of many applications through the exploitation of otherwise idle execution units within the processor core. The other significant innovation in the POWER5 processor design is the integration of a memory controller onto the processor chip to decrease the latency to memory and improve system reliability. 2.3.2 Vector/SIMD Multimedia eXtension The Vector/SIMD Multimedia eXtension (VMX) is an extension to the PowerPC Architecture. It defines additional registers and instructions to support single-instruction multiple-data (SIMD) operations that accelerate data-intensive tasks. The VMX extensions to the PowerPC Architecture were developed jointly by Apple Computer, IBM, and Motorola. Apple Computer and Motorola use different terminology to refer to the VMX extensions of the PowerPC Architecture. Specifically, Motorola uses the term Altivec, and Apple uses the term Velocity Engine. A short vector processing history The basic concept behind vector processing is to enhance the performance of data-intensive applications by providing hardware support for operations that can manipulate an entire vector (or array) of data in a single operation. The number of data elements operated upon at a time is called the vector length. 38 The IBM Eserver BladeCenter JS20
Scalar processors perform operations that manipulate single data elements such as fixed-point or floating-point numbers. For example, scalar processors usually have an instruction that adds two integers to produce a single-integer result. Vector processors perform operations on multiple data elements arranged in groups called vectors (or arrays). For example, a vector add operation to add two vectors performs a pairwise addition of each element of one source vector with the corresponding element of the other source vector. It places the result in the corresponding element of the destination vector. Typically a single vector operation on vectors of length n is equivalent to performing n scalar operations. Figure 2-10 illustrates the difference between scalar and vector operations. Scalar Add Operation 7 1 4 + 7 11 6 3 3 10 + Figure 2-10 Scalar and vector operations Vector Add Operation Processor designers are continually looking for ways to improve application performance. The addition of vector operations to a processor architecture is one method that a processor designer can use to make it easier to improve the peak performance of a processor. However, the actual performance improvements that can be obtained for a specific application depend on how well the application can exploit vector operations. The concept of vector processing has existed since the 1950s. Early implementations of vector processing (known as array processing) were installed in the 1960s. They used special purpose peripherals attached to general purpose computers. An example is the IBM 2938 Array Processor, which could be attached to some models of the IBM System/360. This was followed by the IBM 3838 Array Processor in later years. By the mid-1970s, vector processing became an integral part of the main processor in large supercomputers manufactured by companies such as Cray Research. By the mid-1980s, vector processing became available as an optional feature on large general-purpose computers such as the IBM 3090. In the 1990s, developers of microprocessors used in desktop computers adapted the concept of vector processing to enhance the capability of their microprocessors when running desktop multimedia applications. These 5 6 11 4 5 2 12 7 17 7 8 12 Chapter 2. Hardware components 39
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The IBM Eserver BladeCenter JS20 Le
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Note: Before using this information
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LAN Switch Module in I/O Module Bay
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e. Leave the values for User Define
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connections. This is sufficient to
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minutes, you are disconnected. You
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6. As soon as you type 8, the Open
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5. Select the JS20 blade that you a
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6.1 Installing Linux Both Red Hat E
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SuSE sources SuSE installations are
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3. In the next panel as shown in Fi
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To build your own zImage.initrd, fo
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6.2.1 BOOTP DHCP is an extension to
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6.3.1 Red Hat Kickstart Red Hat pro
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6.3.2 SuSE AutoYaST SLES provides a
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► System Set the general system i
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The syntax for mkzimage_cmdline is
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3. We select the install option and
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7.1 Minimal NIM installation Follow
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4. In the next window (Figure 7-4),
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3. In the Configure NIM Environment
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7.3 Adding machine information With
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3. In the next window (Figure 7-12)
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7.4 Preparing the NIM master With a
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1. On the first panel, select the d
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4. As illustrated in Figure 7-19, w
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8.1 IBM Director IBM Director is a
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8.1.1 Setting up an IBM Director Se
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8. Enter the database connection in
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2. With the sources copied to the h
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As CSM was being developed, the Ext
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This is the interface that will be
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version packaged with CSM. And you
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You can verify what user IDs you co
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► PowerMethod: Should always be b
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The csmsetupyast command uses an XM
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RHEL Red Hat Enterprise Linux RISC
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Online resources ► CSM for Linux:
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How to get IBM Redbooks Help from I
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eth0 62 eth1 62 F Fibre Channel Exp
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T translation lookaside buffer (TLB
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The IBM Eserver BladeCenter JS20 Le
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The IBM eServer BladeCenter JS20 - IBM Redbooks

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