The IBM eServer BladeCenter JS20 - IBM Redbooks

The architecture also features a condition register that is set by the result of fixed
or floating point computational instructions and that can be used to control
branch processing. Branch instructions also make use of a count and a link
register.
Figure 2-9 illustrates the complete set of architected PowerPC registers used by
application programs.
CR
0 31
LR
0 63
CTR
0 63
GPR0
GPR1
...
GPR31
0 63
XER
0 63
FPR0
FPR1
...
FPR31
0 63
FPSCR
0 31
Condition Register
Link Register
Count Register
General Purpose Registers
Figure 2-9 PowerPC registers used by application programs
Fixed-Point Exception Register
Floating-Point Registers
Floating-Point Status
and Control Register
In the PowerPC Architecture, fixed and floating-point computational instructions
can operate on operands stored in registers. Data must be loaded from memory
into a register using a fixed or floating-point load instruction before computations
can be performed. Similarly, data must be stored from a register into memory
using an explicit fixed or floating-point store instruction once computation is
completed. This behavior is also characteristic of a RISC architecture.
Chapter 2. Hardware components 35