The IBM eServer BladeCenter JS20 - IBM Redbooks

The speculative superscalar techniques used in the PowerPC 970 include:
► Aggressive branch prediction
– Prediction for up to two branches per cycle
– Support for up to 16 predicted branches in flight
– Prediction support for both branch direction and branch addresses
► In order dispatch of up to five operations into a distributed issue queue
structure per cycle
► Out of order issue of up to ten operations into ten execution pipelines per
cycle, comprised of:
– Two load or store operations
– Two fixed-point register-to-register operations
– Two floating-point operations
– One branch operation
– One condition register operation
– One VMX permute operation
– One VMX arithmetic operation
► Register renaming on most architected PowerPC registers including the
GPRs, FPRs, VRFs, condition register fields, FPSCR, VSCR, the link register
(LR), and the count register (CTR)
The total number of in-flight instructions within the processor core at any point in
time can be as high as 215.
The VMX execution units operate on multiple data elements concurrently.
Therefore, they provide a performance equivalent to multiple scalar execution
units.
Bus Interface Unit
The interface between the PowerPC 970 and external devices is provided by the
Bus Interface Unit (BIU). The interface is comprised of two unidirectional paths
(one in, one out) that are each four bytes wide.
The internal processor clock operates at an integral multiple of the interface
speed. On the BladeCenter JS20, the processor clock operates at double the
interface speed.
The total aggregate transfer rate across the interface in bytes per second is four
times of the processor clock speed (1/2 x 2 x 4). This equates to 6.4 GBps for
processors operating at 1.6 GHz, and 8.8 GBps for processors operating at
2.2 GHz.
The interface is multiplexed, with both addresses and data being transferred
across the same wires. Therefore the peak theoretical data throughput across
Chapter 2. Hardware components 45