The IBM eServer BladeCenter JS20 - IBM Redbooks

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The major features of the PowerPC 970 include: ► Speculative, superscalar RISC processor core with vector extensions ► On-chip level-1 and level-2 caches ► Deeply pipelined design up to 25 stages long ► Aggressive branch prediction ► In order dispatch of up to five operations per cycle ► Out of order issue of up to ten operations per cycle ► In order completion of up to five operations per cycle ► Register renaming ► Up to 215 instructions in-flight ► Fast selective flush of incorrect speculative instructions and results ► Hardware prefetching of up to eight streams including four VMX streams We elaborate on some of these features in the following sections. Cache structure The PowerPC 970 includes several on-chip caches to reduce memory latency when fetching instructions and performing data load and store operations. Understanding the structure of these caches is sometimes useful when doing low-level assembly language programming. The on-chip caches include: ► 64 KB, direct-mapped instruction cache ► 32 KB, 2-way set associative data cache ► 128-entry, instruction effective to real address translation (ERAT) cache instructions ► 128-entry, data ERAT cache ► 64-entry, fully associative segment lookaside buffer (SLB) ► 1024-entry, 4-way set associative translation lookaside buffer (TLB) ► 512 KB, 8-way set associative, level-2 cache Speculative superscalar features The design of the PowerPC 970 uses a variety of techniques to enable superscalar operation, where multiple instructions are executed during each processor clock cycle. This capability is enabled by the exploitation of multiple execution units within the processor core. 44 The IBM Eserver BladeCenter JS20
The speculative superscalar techniques used in the PowerPC 970 include: ► Aggressive branch prediction – Prediction for up to two branches per cycle – Support for up to 16 predicted branches in flight – Prediction support for both branch direction and branch addresses ► In order dispatch of up to five operations into a distributed issue queue structure per cycle ► Out of order issue of up to ten operations into ten execution pipelines per cycle, comprised of: – Two load or store operations – Two fixed-point register-to-register operations – Two floating-point operations – One branch operation – One condition register operation – One VMX permute operation – One VMX arithmetic operation ► Register renaming on most architected PowerPC registers including the GPRs, FPRs, VRFs, condition register fields, FPSCR, VSCR, the link register (LR), and the count register (CTR) The total number of in-flight instructions within the processor core at any point in time can be as high as 215. The VMX execution units operate on multiple data elements concurrently. Therefore, they provide a performance equivalent to multiple scalar execution units. Bus Interface Unit The interface between the PowerPC 970 and external devices is provided by the Bus Interface Unit (BIU). The interface is comprised of two unidirectional paths (one in, one out) that are each four bytes wide. The internal processor clock operates at an integral multiple of the interface speed. On the BladeCenter JS20, the processor clock operates at double the interface speed. The total aggregate transfer rate across the interface in bytes per second is four times of the processor clock speed (1/2 x 2 x 4). This equates to 6.4 GBps for processors operating at 1.6 GHz, and 8.8 GBps for processors operating at 2.2 GHz. The interface is multiplexed, with both addresses and data being transferred across the same wires. Therefore the peak theoretical data throughput across Chapter 2. Hardware components 45
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The IBM Eserver BladeCenter JS20 Le
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Note: Before using this information
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Chapter 4. Planning considerations
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6-8 Language selection . . . . . .
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minutes, you are disconnected. You
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6. As soon as you type 8, the Open
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5. Select the JS20 blade that you a
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6.1 Installing Linux Both Red Hat E
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SuSE sources SuSE installations are
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3. In the next panel as shown in Fi
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To build your own zImage.initrd, fo
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6.2.1 BOOTP DHCP is an extension to
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6.3.1 Red Hat Kickstart Red Hat pro
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6.3.2 SuSE AutoYaST SLES provides a
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► System Set the general system i
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The syntax for mkzimage_cmdline is
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3. We select the install option and
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7.1 Minimal NIM installation Follow
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4. In the next window (Figure 7-4),
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3. In the Configure NIM Environment
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7.3 Adding machine information With
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3. In the next window (Figure 7-12)
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7.4 Preparing the NIM master With a
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1. On the first panel, select the d
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4. As illustrated in Figure 7-19, w
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8.1 IBM Director IBM Director is a
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8.1.1 Setting up an IBM Director Se
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8. Enter the database connection in
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2. With the sources copied to the h
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As CSM was being developed, the Ext
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This is the interface that will be
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version packaged with CSM. And you
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You can verify what user IDs you co
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► PowerMethod: Should always be b
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The csmsetupyast command uses an XM
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RHEL Red Hat Enterprise Linux RISC
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Online resources ► CSM for Linux:
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How to get IBM Redbooks Help from I
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eth0 62 eth1 62 F Fibre Channel Exp
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T translation lookaside buffer (TLB
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The IBM Eserver BladeCenter JS20 Le
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