The IBM eServer BladeCenter JS20 - IBM Redbooks

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IBM processors implementing PowerPC Architecture Since IBM teamed with Motorola and Apple Computer to define PowerPC Architecture, IBM has developed many different processors that implement this architecture. These processors fall into two main categories: ► Processors that are used as the main processor within IBM workstations and servers ► Processors that IBM produces for embedding in a wide variety of computing and non-computing devices We focus our review of IBM processors implementing PowerPC Architecture on those processors that are used as the main processors within IBM workstations and servers. 32-bit PowerPC processors In the early 1990s, IBM jointly designed with Motorola a series of 32-bit PowerPC processors with the designation 60X that were used in IBM RS/6000 workstations and servers. They were also used in computer systems from other computer manufacturers such as Apple Computer. The first of these was the PowerPC 601®. It debuted in the IBM RS/6000 Model 250 in 1993. The PowerPC 601 was an evolution of the RISC Single Chip implementation of the POWER processor and did not implement the full PowerPC Architecture. It represented a transition between the earlier POWER architecture and the PowerPC Architecture. The PowerPC 601 was subsequently followed by the PowerPC 603 and PowerPC 604. These represented full implementations of the 32-bit PowerPC Architecture. Enhanced versions of these processors known as the PowerPC 603e and PowerPC 604e were subsequently introduced. The PowerPC 603 was an entry-level processor. The PowerPC 604 was a high-end processor and introduced support for symmetrical multi-processor (SMP) configurations. RS64 processors In 1997, IBM introduced its first servers that incorporated processors based on the 64-bit PowerPC Architecture. These processors were called the RS64. The RS64 was subsequently enhanced with the introduction of the RS64-II, RS64-III, and RS64-IV in later years. The RS64-IV operated at processor clock speeds as high as 750 MHz. The RS64 processor and its successors were optimized for use in commercial applications and de-emphasized the floating point capabilities of the earlier POWER2 processors. The RS64 processors were used in both IBM RS/6000 36 The IBM Eserver BladeCenter JS20
(later IBM Eserver pSeries®) and IBM AS/400® (later IBM Eserver iSeries) servers, most frequently in SMP configurations, with some as large as 24 processors. POWER3 and POWER3-II processors The POWER3 processor was first used in IBM RS/6000 servers and workstations introduced in 1998. The POWER3 processor continued the evolution of the excellent floating-point performance provided by the POWER2 Super Chip (P2SC) processor, while implementing 64-bit PowerPC Architecture and supporting SMP configurations of up to 16 processors. Upon introduction, the POWER3 processor operated at 200 MHz, and delivered peak floating-point performance of 800 MFLOPS per processor. An improved version of the POWER3 processor, known as the POWER3-II, was subsequently introduced. The POWER3-II featured processor clock speeds as high as 450 MHz, and delivered peak floating point performance of 1.8 GFLOPS per processor. You can learn more about the POWER3 processor in the IBM white paper POWER3: Next Generation 64-bit PowerPC Processor Design, which is available on the Web at: http://www.ibm.com/servers/eserver/pseries/hardware/whitepapers/power3wp.html POWER4 and POWER4+ processors The POWER4 processor combined the best attributes of both the RS64 and POWER3 processors. It delivers a 64-bit PowerPC Architecture processor that is capable of delivering high levels of performance in both commercial and scientific applications. The POWER4 processor is the first PowerPC Architecture processor to feature multiple processor cores on a single chip. Each POWER4 processor chip has two independent processor cores and a shared level-2 cache. The original POWER4 processor operated at processor clock speeds as high as 1.3 GHz and has featured in SMP configurations as large as 32 processor cores. An enhanced version of the POWER4 processor, known as the POWER4+, was subsequently introduced and installed at processor clock speeds as high as 1.9 GHz in the 32 processor core IBM Eserver pSeries Model 690. You can learn more about the POWER4 processor in the IBM white paper entitled POWER4 System Microarchitecture, which is available on the Web at: http://www.ibm.com/servers/eserver/pseries/hardware/whitepapers/power4.html Chapter 2. Hardware components 37
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The IBM Eserver BladeCenter JS20 Le
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Page 10 and 11: 6-8 Language selection . . . . . .
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Page 14 and 15: Trademarks The following terms are
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Page 22 and 23: for e-commerce and On Demand Busine
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1. Download the firmware update pac
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LAN Switch Module in I/O Module Bay
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e. Leave the values for User Define
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connections. This is sufficient to
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minutes, you are disconnected. You
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6. As soon as you type 8, the Open
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5. Select the JS20 blade that you a
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100 The IBM Eserver BladeCenter JS2
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6.1 Installing Linux Both Red Hat E
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SuSE sources SuSE installations are
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3. In the next panel as shown in Fi
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To build your own zImage.initrd, fo
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6.2.1 BOOTP DHCP is an extension to
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6.3.1 Red Hat Kickstart Red Hat pro
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6.3.2 SuSE AutoYaST SLES provides a
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► System Set the general system i
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The syntax for mkzimage_cmdline is
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3. We select the install option and
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7.1 Minimal NIM installation Follow
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4. In the next window (Figure 7-4),
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3. In the Configure NIM Environment
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7.3 Adding machine information With
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3. In the next window (Figure 7-12)
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7.4 Preparing the NIM master With a
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1. On the first panel, select the d
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4. As illustrated in Figure 7-19, w
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8.1 IBM Director IBM Director is a
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8.1.1 Setting up an IBM Director Se
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8. Enter the database connection in
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2. With the sources copied to the h
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As CSM was being developed, the Ext
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This is the interface that will be
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version packaged with CSM. And you
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You can verify what user IDs you co
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► PowerMethod: Should always be b
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The csmsetupyast command uses an XM
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RHEL Red Hat Enterprise Linux RISC
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Online resources ► CSM for Linux:
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How to get IBM Redbooks Help from I
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eth0 62 eth1 62 F Fibre Channel Exp
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T translation lookaside buffer (TLB
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The IBM Eserver BladeCenter JS20 Le
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