The IBM eServer BladeCenter JS20 - IBM Redbooks
The IBM eServer BladeCenter JS20 - IBM Redbooks
The IBM eServer BladeCenter JS20 - IBM Redbooks
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(later <strong>IBM</strong> Eserver pSeries®) and <strong>IBM</strong> AS/400® (later <strong>IBM</strong> Eserver iSeries)<br />
servers, most frequently in SMP configurations, with some as large as 24<br />
processors.<br />
POWER3 and POWER3-II processors<br />
<strong>The</strong> POWER3 processor was first used in <strong>IBM</strong> RS/6000 servers and<br />
workstations introduced in 1998. <strong>The</strong> POWER3 processor continued the<br />
evolution of the excellent floating-point performance provided by the POWER2<br />
Super Chip (P2SC) processor, while implementing 64-bit PowerPC Architecture<br />
and supporting SMP configurations of up to 16 processors.<br />
Upon introduction, the POWER3 processor operated at 200 MHz, and delivered<br />
peak floating-point performance of 800 MFLOPS per processor. An improved<br />
version of the POWER3 processor, known as the POWER3-II, was subsequently<br />
introduced. <strong>The</strong> POWER3-II featured processor clock speeds as high as 450<br />
MHz, and delivered peak floating point performance of 1.8 GFLOPS per<br />
processor.<br />
You can learn more about the POWER3 processor in the <strong>IBM</strong> white paper<br />
POWER3: Next Generation 64-bit PowerPC Processor Design, which is available<br />
on the Web at:<br />
http://www.ibm.com/servers/eserver/pseries/hardware/whitepapers/power3wp.html<br />
POWER4 and POWER4+ processors<br />
<strong>The</strong> POWER4 processor combined the best attributes of both the RS64 and<br />
POWER3 processors. It delivers a 64-bit PowerPC Architecture processor that is<br />
capable of delivering high levels of performance in both commercial and scientific<br />
applications.<br />
<strong>The</strong> POWER4 processor is the first PowerPC Architecture processor to feature<br />
multiple processor cores on a single chip. Each POWER4 processor chip has<br />
two independent processor cores and a shared level-2 cache.<br />
<strong>The</strong> original POWER4 processor operated at processor clock speeds as high as<br />
1.3 GHz and has featured in SMP configurations as large as 32 processor cores.<br />
An enhanced version of the POWER4 processor, known as the POWER4+, was<br />
subsequently introduced and installed at processor clock speeds as high as<br />
1.9 GHz in the 32 processor core <strong>IBM</strong> Eserver pSeries Model 690.<br />
You can learn more about the POWER4 processor in the <strong>IBM</strong> white paper<br />
entitled POWER4 System Microarchitecture, which is available on the Web at:<br />
http://www.ibm.com/servers/eserver/pseries/hardware/whitepapers/power4.html<br />
Chapter 2. Hardware components 37