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374 3. Reference Manual
Linear resistors (R), capacitors (C), and inductors (L) are converted to their generic counterpart in
Analog Insydes. Model calls are generated if temperature dependencies are given or a model is
defined.
Linear controlled sources (E, F, G, H) are converted to their generic counterpart in Analog Insydes. In
case of current controlled sources (F, H) additional nodes are introduced. In case of nonlinear voltage
controlled sources (E, G) a behavioral model is generated and appended to the netlist. Supported
types are POLY, VALUE, and TABLE.
Independent sources (I, V) of type EXP, PULSE, PWL, SFFM, and SIN are supported (see Chapter 4.1).
Parameterized subcircuits are also supported and may contain local model cards and local subcircuit
definitions.
For calls to HDLA models (Y), ReadNetlist reads the file "hdlaInfo" and scans the section
[HdlaPins] to set up the correct node to port mapping:
{rd, {n 1 −> p 1 , },
Model −> Model[entity, architecture, rd],
Selector −> architecture, }
with the HDLA entity name entity and the HDLA architecture name architecture. If the file cannot
be found a generic port list is generated:
{rd, {n 1 −> 1, n 2 −> 2, }
Model −> Model[entity, architecture, rd],
Selector −> architecture, }
The environment variables HDLALIBPATH and HDLAWORKPATH are taken into account while searching
for the file "hdlaInfo".
The following cards are supported: