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2.2 Netlists 41<br />

1<br />

CM<br />

2<br />

V0<br />

RB<br />

RL<br />

IB<br />

beta*IB<br />

Figure 2.6: Result of incorrectly inserted current-controlled current source<br />

The correct solution to this problem is to add another node to the circuit and connect the controlling<br />

branch in series with RB as shown in Figure 2.7.<br />

1<br />

CM<br />

2<br />

V0<br />

3<br />

IB<br />

RB<br />

beta*IB<br />

RL<br />

Figure 2.7: CCCS circuit with correctly inserted controlling branch<br />

We can then write a correct netlist as follows:<br />

In[8]:= cccsCircuit =<br />

Netlist[<br />

{V0, {1, 0}, V0},<br />

{RB, {1, 3}, RB},<br />

{CM, {1, 2}, CM},<br />

{CC1, {3, 0, 2, 0}, beta},<br />

{RL, {2, 0}, RL}<br />

]<br />

Out[8]= NetlistRaw, 5 <br />

2.2.3 A Brief Preview on Circuit Analysis<br />

There is much more to learn about netlists, but before going into the details let’s get an impression of<br />

Analog Insydes’ basic symbolic circuit analysis functionality. Computing voltages and currents in a<br />

circuit requires essentially two steps: Setting up a system of circuit equations and then solving these<br />

equations. Circuit equations can be set up automatically by applying the function CircuitEquations<br />

(Section 3.5.1) to a netlist description.<br />

We set up equations for the voltage divider circuit defined in Section 2.2.1 (see Figure 2.1):

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