IntelÂ® Extended Memory 64 Technology Software Developer's Guide

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Compatibility Mode ExceptionsSame as protected mode exceptions.64-Bit Mode Exceptions#SS(0)If a memory address referencing the SS segment is in a non-canonical form.#GP(0)If the memory address is in a non-canonical form.If memory operand is not aligned on a 16-byte boundary, regardless of segment.#PF(fault-code) For a page fault.#NMIf TS in CR0 is set.#XM If an unmasked SIMD floating-point exception and OSXMMEXCPT in CR4 is 1.#UD If an unmasked SIMD floating-point exception and OSXMMEXCPT in CR4 is 0.If EM in CR0 is set.If OSFXSR in CR4 is 0.If CPUID feature flag SSE is 0.2-74 Vol. 1
CMPS/CMPSB/CMPSW/CMPSD/CMPSQ—Compare String OperandsOpcode Instruction 64-Bit Mode Compat/Leg DescriptionModeA6 CMPS m8, m8 Valid Valid For legacy mode, compare byte at addressES:(E)SI; For 64-bit mode compare byte at address(R)SI. The status flags are set accordingly.A7 CMPS m16, m16 Valid Valid For legacy mode, compare word at addressES:(E)SI; For 64-bit mode compare word at address(R)SI. The status flags are set accordingly.A7 CMPS m32, m32 Valid Valid For legacy mode, compare dword at addressES:(E)SI; For 64-bit mode compare dword ataddress (R)SI. The status flags are set accordingly.REX.W + A7 CMPS m64, m64 Valid N.E. Compares quadword at address RSI with quadwordat address RDI and sets the status flags accordinglyA6 CMPSB Valid Valid For legacy mode, compare byte at addressES:(E)SI; For 64-bit mode compare byte at address(R)SI. The status flags are set accordingly.A7 CMPSW Valid Valid For legacy mode, compare word at addressES:(E)SI; For 64-bit mode compare word at address(R)SI. The status flags are set accordingly.A7 CMPSD Valid Valid For legacy mode, compare dword at addressES:(E)SI; For 64-bit mode compare dword ataddress (R)SI. The status flags are set accordingly.REX.W + A7 CMPSD Valid N.E. Compares quadword at address RSI with quadwordat address RDI and sets the status flags accordinglyFlags AffectedThe CF, OF, SF, ZF, AF, and PF flags are set according to the temporary result of the comparison.IA-32e Mode OperationInstruction is promoted to 64-bits.Default Operation Size is 32 bitsProtected Mode Exceptions#GP(0)#SS(0)#PF(fault-code)#AC(0)If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.If the DS, ES, FS, or GS register contains a null segment selector.If a memory operand effective address is outside the SS segment limit.If a page fault occurs.If alignment checking is enabled and an unaligned memory reference is made while thecurrent privilege level is 3.Real-Address Mode Exceptions#GP#SSIf a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.If a memory operand effective address is outside the SS segment limit.Vol. 1 2-75
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Intel ® Extended Memory 64 Technol
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1.6.9.1. Call Gates. . . . . . . .
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FSUB/FSUBP/FISUB—Subtract . . . .
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PADDSB/PADDSW—Add Packed Signed I
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-xii Vol. 1
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ModeIA-32emodeOperatingSystemRequir
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1.3. REGISTER-SET CHANGESThis secti
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Table 1-4 IA32_EFER Bit Description
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IA-32e sub-modeTable 1-8 64-Bit Ext
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REX PREFIX0100WR0BOpcodemod!=11ModR
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1.4.2.4. Direct Memory-Offset MOVsI
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The 64-bit default operation-size e
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1.6.2. Register Settings and IA-32e
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1.6.3.4. Compatibility ModeCompatib
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• When in compatibility mode, FS
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Prior to activating IA-32e mode, PA
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Table 1-22 through Table 1-24 shows
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Table 1-26 Reserved Bit CheckingMod
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• Bits 29:21 index into the 512-e
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Only 64-bit mode call gates can be
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Although the hardware task-switchin
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Table 1-39 IA-32e Mode Interrupt an
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If the IST index for an interrupt g
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1-38 Vol. 1
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• ib, iw, id, io — A 1-byte (ib
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• m16:16, m16:32 & m16:64 —A me
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which is either 16, 32 or 64-bits.
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2.1.3.1. IA-32e Mode OperationThe s
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2.1.10. SIMD Floating-Point Excepti
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AAD—ASCII Adjust AX Before Divisi
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AAS—ASCII Adjust AL After Subtrac
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Real-Address Mode Exceptions#GPIf a
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64-Bit Mode Exceptions#SS(0)If a me
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Page 74 and 75: 64-Bit Mode Exceptions#SS(0)If a me
Page 82 and 83: Real-Address Mode Exceptions#GPIf a
Page 84 and 85: #PF(fault-code)#NM#UDFor a page fau
Page 92 and 93: BOUND—Check Array Index Against B
Page 94 and 95: BSF—Bit Scan ForwardOpcode Instru
Page 96 and 97: BSWAP—Byte SwapOpcode Instruction
Page 98 and 99: #AC(0)If alignment checking is enab
Page 100 and 101: #GP(0)#PF(fault-code)#AC(0)If the m
Page 102 and 103: #PF(fault-code)#AC(0)If a page faul
Page 104: 64-Bit Mode Exceptions#SS(0)If a me
Page 107 and 108: Compatibility Mode ExceptionsSame a
Page 109 and 110: CDQ—Convert Double to QuadSee ent
Page 111 and 112: CLD—Clear Direction FlagOpcode In
Page 113 and 114: CLI—Clear Interrupt FlagOpcode In
Page 115 and 116: CMC—Complement Carry FlagOpcode I
Page 117 and 118: Opcode Instruction 64-Bit Mode Comp
Page 119 and 120: CMP—Compare Two OperandsOpcode In
Page 121 and 122: CMPPD—Compare Packed Double-Preci
Page 123: CMPPS—Compare Packed Single-Preci
Page 127 and 128: CMPSD—Compare Scalar Double-Preci
Page 129 and 130: CMPSS—Compare Scalar Single-Preci
Page 131 and 132: CMPXCHG—Compare and ExchangeOpcod
Page 133 and 134: CMPXCHG8B/CMPXCHG16B—Compare and
Page 135 and 136: COMISD—Compare Scalar Ordered Dou
Page 137 and 138: COMISS—Compare Scalar Ordered Sin
Page 139 and 140: CPUID—CPU IdentificationOpcode In
Page 141 and 142: Initial EAXValue80000005H80000006H8
Page 143 and 144: Table 2-8 CPUID Feature Information
Page 145 and 146: • The most significant bit (bit 3
Page 147 and 148: Table 2-10 Brand String Offsets (Co
Page 149 and 150: CVTDQ2PD—Convert Packed Doublewor
Page 151 and 152: CVTDQ2PS—Convert Packed Doublewor
Page 153 and 154: CVTPD2DQ—Convert Packed Double-Pr
Page 155 and 156: CVTPD2PI—Convert Packed Double-Pr
Page 157 and 158: CVTPD2PS—Covert Packed Double-Pre
Page 159 and 160: CVTPI2PD—Convert Packed Doublewor
Page 161 and 162: CVTPI2PS—Convert Packed Doublewor
Page 163 and 164: CVTPS2DQ—Convert Packed Single-Pr
Page 165 and 166: CVTPS2PD—Covert Packed Single-Pre
Page 167 and 168: CVTPS2PI—Convert Packed Single-Pr
Page 169 and 170: CVTSD2SI—Convert Scalar Double-Pr
Page 171 and 172: CVTSD2SS—Convert Scalar Double-Pr
Page 173 and 174: CVTSI2SD—Convert Doubleword Integ
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CVTSI2SS—Convert Doubleword Integ
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CVTSS2SD—Convert Scalar Single-Pr
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CVTSS2SI—Convert Scalar Single-Pr
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CVTTPD2PI—Convert with Truncation
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CVTTPD2DQ—Convert with Truncation
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CVTTPS2DQ—Convert with Truncation
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CVTTPS2PI—Convert with Truncation
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CVTTSD2SI—Convert with Truncation
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CVTTSS2SI—Convert with Truncation
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CWD/CDQ/CQQ—Convert Word to Doubl
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DAS—Decimal Adjust AL after Subtr
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Virtual-8086 Mode Exceptions#DE If
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ENTER—Make Stack Frame for Proced
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FABS—Absolute ValueOpcode Instruc
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Virtual-8086 Mode Exceptions#GP(0)I
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FCLEX/FNCLEX—Clear ExceptionsOpco
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FCOM/FCOMP/FCOMPP—Compare Floatin
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FCOMI/FCOMIP/ FUCOMI/FUCOMIP—Comp
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FDECSTP—Decrement Stack-Top Point
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FICOM/FICOMP—Compare IntegerOpcod
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FILD—Load IntegerOpcode Instructi
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FINCSTP—Increment Stack-Top Point
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FIST/FISTP—Store IntegerOpcode In
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FISTTP—Store Integer with Truncat
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FLD—Load Floating Point ValueOpco
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FLD1/FLDL2T/FLDL2E/FLDPI/FLDLG2/FLD
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Compatibility Mode ExceptionsSame a
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FPATAN—Partial ArctangentOpcode I
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FPREM1—Partial RemainderOpcode In
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FRNDINT—Round to IntegerOpcode In
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FSIN—SineOpcode Instruction 64-Bi
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FSQRT—Square RootOpcode Instructi
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Protected Mode Exceptions#GP(0)If a
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Protected Mode Exceptions#GP(0)If a
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FUCOM/FUCOMP/FUCOMPP—Unordered Co
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FXAM—ExamineOpcode Instruction 64
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FXRSTOR—Restore x87 FPU, MMX, SSE
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FXSAVE—Save x87 FPU, MMX, SSE, an
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XMM0 throughXMM7XMM registers (128
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Table 2-14 Layout of the 64-bit FXS
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Protected Mode Exceptions#GP(0)For
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FXTRACT—Extract Exponent and Sign
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FYL2XP1—Compute y ∗ log 2 (x +1
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HSUBPD—Horizontal Subtract Packed
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HSUBPS—Horizontal Subtract Packed
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IDIV—Signed DivideOpcode Instruct
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IMUL—Signed MultiplyOpcode Instru
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IN—Input from PortOpcode Instruct
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Compatibility Mode ExceptionsSame a
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INVD—Invalidate Internal CachesOp
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IRET/IRETD—Interrupt ReturnOpcode
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Jcc—Jump if Condition Is MetOpcod
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Opcode Instruction 64-Bit Mode Comp
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#SS(0)#NP (selector)#PF(fault-code)
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LAHF—Load Status Flags into AH Re
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LDDQU—Load Unaligned Double Quadw
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LDMXCSR—Load MXCSR RegisterOpcode
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LDS/LES/LFS/LGS/LSS—Load Far Poin
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LEA—Load Effective AddressOpcode
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LES—Load Full PointerSee entry fo
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LFS—Load Full PointerSee entry fo
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LGS—Load Full PointerSee entry fo
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LMSW—Load Machine Status WordOpco
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LODS/LODSB/LODSW/LODSD/LODSQ—Load
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LOOP/LOOPcc—Loop According to ECX
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LSS—Load Full PointerSee entry fo
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