Intel® Extended Memory 64 Technology Software Developer's Guide

Although the hardware task-switching mechanism is not supported in IA-32e mode, a 64-bit task state segment (TSS)must still exist. Table 1-37 shows the format of a 64-bit TSS. This 64-bit field holds information important to IA-32emode and is not directly related to the task-switch mechanism. These are:• RSPn; the full 64-bit canonical forms of the stack pointers (RSP) for privilege levels 0–2• ISTn; the full 64-bit canonical forms of the interrupt stack table (IST, see Section 1.6.10.4.) pointers• I/O Map Base Address; the 16-bit offset to the I/O permission bit map from the 64-bit TSS baseThe operating system must create at least one 64-bit TSS after activating IA-32e mode. It must execute the LTRinstruction (in 64-bit mode) to load the TR register with a pointer to the 64-bit TSS responsible for both 64-bit-modeprograms and compatibility-mode programs.Table 1-37 TSS Format in IA-32e ModeByte Offset 31:16 15:0+64H I/O Map Base Reserved+60H Reserved+5CH Reserved+58H IST7 (upper 32-bits)+54H IST7 (lower 32-bits)+50H IST6 (upper 32-bits)+4CH IST6 (lower 32-bits)+48H IST5 (upper 32-bits)+44H IST5 (lower 32-bits)+40H IST4 (upper 32-bits)+3CH IST4 (lower 32-bits)+38H IST3 (upper 32-bits)+34H IST3 (lower 32-bits)+30H IST2 (upper 32-bits)+2CH IST2 (lower 32-bits)+28H IST1 (upper 32-bits)+24H IST1 (lower 32-bits)+20H Reserved+1CH Reserved+18H RSP2 (upper 32-bits)+14H RSP2 (lower 32-bits)+10H RSP1 (upper 32-bits)+0CH RSP1 (lower 32-bits)+08H RSP0 (upper 32-bits)+04H RSP0 (lower 32-bits)00H Reserved1-32 Vol. 1