Intel® Extended Memory 64 Technology Software Developer's Guide

CMPXCHG8B/CMPXCHG16B—Compare and Exchange 8 BytesOpcode Instruction 64-Bit Mode Compat/Leg DescriptionMode0F C7 /1 m64 CMPXCHG8B m64 Valid Valid Compare EDX:EAX with m64. Ifequal, set ZF and load ECX:EBXinto m64. Else, clear ZF and loadm64 into EDX:EAX.REX.W + 0F C7 /1 m128 CMPXCHG16B m128 Valid N.E. Compare RDX:RAX with m128. Ifequal, set ZF and load RCX:RBXinto m128. Else, clear ZF and loadm128 into RDX:RAX.Flags AffectedThe ZF flag is set if the destination operand and EDX:EAX are equal; otherwise it is cleared. The CF, PF, AF, SF, andOF flags are unaffected.IA-32e Mode OperationPromoted to 64-bitsDefault Operation Size is 64-bits.CMPXCHG16B requires that the destination (memory) operand be 16-byte-aligned.Protected Mode Exceptions#UD#GP(0)#SS(0)#PF(fault-code)#AC(0)If the destination operand is not a memory location.If the destination is located in a nonwritable segment.If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.If the DS, ES, FS, or GS register contains a null segment selector.If a memory operand effective address is outside the SS segment limit.If a page fault occurs.If alignment checking is enabled and an unaligned memory reference is made while thecurrent privilege level is 3.Real-Address Mode Exceptions#UD#GP#SSIf the destination operand is not a memory location.If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.If a memory operand effective address is outside the SS segment limit.Virtual-8086 Mode Exceptions#UD#GP(0)#SS(0)#PF(fault-code)#AC(0)If the destination operand is not a memory location.If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.If a memory operand effective address is outside the SS segment limit.If a page fault occurs.If alignment checking is enabled and an unaligned memory reference is made.Vol. 1 2-83