IntelÂ® Extended Memory 64 Technology Software Developer's Guide

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<strong>64</strong>-Bit Mode Exceptions#SS(0)If a memory address referencing the SS segment is in a non-canonical form.#GP(0)If the memory address is in a non-canonical form.#NMIf TS in CR0 is set.#UDIf EM in CR0 is set.If OSFXSR in CR4 is 0.If CPUID feature flag SSE3 is 0.#PF(fault-code) If a page fault occurs.2-278 Vol. 1
LDMXCSR—Load MXCSR RegisterOpcode Instruction <strong>64</strong>-Bit Mode Compat/Leg DescriptionMode0F,AE,/2 LDMXCSR m32 Valid Valid Load MXCSR register from m32.IA-32e Mode OperationSame as legacy mode.C/C++ Compiler Intrinsic Equivalent_mm_setcsr(unsigned int i)Numeric ExceptionsNone.Protected Mode Exceptions#GP(0)#SS(0)#PF(fault-code)#NM#UD#AC(0)For an illegal memory operand effective address in the CS, DS, ES, FS, or GS segments.For an attempt to set reserved bits in MXCSR.For an illegal address in the SS segment.For a page fault.If TS in CR0 is set.If EM in CR0 is set.If OSFXSR in CR4 is 0.If CPUID feature flag SSE is 0.If alignment checking is enabled and an unaligned memory reference is made while thecurrent privilege level is 3.Real Address Mode Exceptions#GP(0)#GP(0)#NM#UDFor an attempt to set reserved bits in MXCSR.If any part of the operand would lie outside of the effective address space from 0 to FFFFH.If TS in CR0 is set.If EM in CR0 is set.If OSFXSR in CR4 is 0.If CPUID feature flag SSE is 0.Virtual 8086 Mode ExceptionsSame exceptions as in Real Address Mode.#PF(fault-code)#AC(0)For a page fault.If alignment checking is enabled and an unaligned memory reference is made.Compatibility Mode ExceptionsSame as for protected mode exceptions.Vol. 1 2-279
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Intel ® Extended Memory 64 Technol
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1.6.9.1. Call Gates. . . . . . . .
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FSUB/FSUBP/FISUB—Subtract . . . .
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PADDSB/PADDSW—Add Packed Signed I
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-xii Vol. 1
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ModeIA-32emodeOperatingSystemRequir
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1.3. REGISTER-SET CHANGESThis secti
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Table 1-4 IA32_EFER Bit Description
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IA-32e sub-modeTable 1-8 64-Bit Ext
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REX PREFIX0100WR0BOpcodemod!=11ModR
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1.4.2.4. Direct Memory-Offset MOVsI
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The 64-bit default operation-size e
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1.6.2. Register Settings and IA-32e
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1.6.3.4. Compatibility ModeCompatib
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• When in compatibility mode, FS
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Prior to activating IA-32e mode, PA
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Table 1-22 through Table 1-24 shows
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Table 1-26 Reserved Bit CheckingMod
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• Bits 29:21 index into the 512-e
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Only 64-bit mode call gates can be
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Although the hardware task-switchin
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Table 1-39 IA-32e Mode Interrupt an
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If the IST index for an interrupt g
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1-38 Vol. 1
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• ib, iw, id, io — A 1-byte (ib
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• m16:16, m16:32 & m16:64 —A me
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which is either 16, 32 or 64-bits.
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2.1.3.1. IA-32e Mode OperationThe s
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2.1.10. SIMD Floating-Point Excepti
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AAD—ASCII Adjust AX Before Divisi
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AAS—ASCII Adjust AL After Subtrac
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Real-Address Mode Exceptions#GPIf a
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64-Bit Mode Exceptions#SS(0)If a me
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#PF(fault-code)#NM#UDFor a page fau
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BOUND—Check Array Index Against B
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BSF—Bit Scan ForwardOpcode Instru
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BSWAP—Byte SwapOpcode Instruction
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#AC(0)If alignment checking is enab
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#GP(0)#PF(fault-code)#AC(0)If the m
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#PF(fault-code)#AC(0)If a page faul
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Compatibility Mode ExceptionsSame a
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CDQ—Convert Double to QuadSee ent
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CLD—Clear Direction FlagOpcode In
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CLI—Clear Interrupt FlagOpcode In
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CMC—Complement Carry FlagOpcode I
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Opcode Instruction 64-Bit Mode Comp
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CMP—Compare Two OperandsOpcode In
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CMPPD—Compare Packed Double-Preci
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CMPPS—Compare Packed Single-Preci
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CMPS/CMPSB/CMPSW/CMPSD/CMPSQ—Comp
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CMPSD—Compare Scalar Double-Preci
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CMPSS—Compare Scalar Single-Preci
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CMPXCHG—Compare and ExchangeOpcod
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CMPXCHG8B/CMPXCHG16B—Compare and
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COMISD—Compare Scalar Ordered Dou
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COMISS—Compare Scalar Ordered Sin
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CPUID—CPU IdentificationOpcode In
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Initial EAXValue80000005H80000006H8
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Table 2-8 CPUID Feature Information
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• The most significant bit (bit 3
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Table 2-10 Brand String Offsets (Co
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CVTDQ2PD—Convert Packed Doublewor
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CVTDQ2PS—Convert Packed Doublewor
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CVTPD2DQ—Convert Packed Double-Pr
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CVTPD2PI—Convert Packed Double-Pr
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CVTPD2PS—Covert Packed Double-Pre
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CVTPI2PD—Convert Packed Doublewor
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CVTPI2PS—Convert Packed Doublewor
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CVTPS2DQ—Convert Packed Single-Pr
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CVTPS2PD—Covert Packed Single-Pre
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CVTPS2PI—Convert Packed Single-Pr
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CVTSD2SI—Convert Scalar Double-Pr
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CVTSD2SS—Convert Scalar Double-Pr
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CVTSI2SD—Convert Doubleword Integ
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CVTSI2SS—Convert Doubleword Integ
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CVTSS2SD—Convert Scalar Single-Pr
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CVTSS2SI—Convert Scalar Single-Pr
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CVTTPD2PI—Convert with Truncation
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CVTTPD2DQ—Convert with Truncation
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CVTTPS2DQ—Convert with Truncation
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CVTTPS2PI—Convert with Truncation
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CVTTSD2SI—Convert with Truncation
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CVTTSS2SI—Convert with Truncation
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CWD/CDQ/CQQ—Convert Word to Doubl
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DAS—Decimal Adjust AL after Subtr
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Virtual-8086 Mode Exceptions#DE If
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ENTER—Make Stack Frame for Proced
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FABS—Absolute ValueOpcode Instruc
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Virtual-8086 Mode Exceptions#GP(0)I
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FCLEX/FNCLEX—Clear ExceptionsOpco
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FCOM/FCOMP/FCOMPP—Compare Floatin
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FCOMI/FCOMIP/ FUCOMI/FUCOMIP—Comp
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FDECSTP—Decrement Stack-Top Point
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FICOM/FICOMP—Compare IntegerOpcod
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FILD—Load IntegerOpcode Instructi
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FINCSTP—Increment Stack-Top Point
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FIST/FISTP—Store IntegerOpcode In
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FISTTP—Store Integer with Truncat
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FLD—Load Floating Point ValueOpco
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FLD1/FLDL2T/FLDL2E/FLDPI/FLDLG2/FLD
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Compatibility Mode ExceptionsSame a
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FPATAN—Partial ArctangentOpcode I
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FPREM1—Partial RemainderOpcode In
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FRNDINT—Round to IntegerOpcode In
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FSIN—SineOpcode Instruction 64-Bi
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FSQRT—Square RootOpcode Instructi
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Protected Mode Exceptions#GP(0)If a
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Protected Mode Exceptions#GP(0)If a
Page 277 and 278: FUCOM/FUCOMP/FUCOMPP—Unordered Co
Page 279 and 280: FXAM—ExamineOpcode Instruction 64
Page 281 and 282: FXRSTOR—Restore x87 FPU, MMX, SSE
Page 283 and 284: FXSAVE—Save x87 FPU, MMX, SSE, an
Page 285 and 286: XMM0 throughXMM7XMM registers (128
Page 287 and 288: Table 2-14 Layout of the 64-bit FXS
Page 289 and 290: Protected Mode Exceptions#GP(0)For
Page 291 and 292: FXTRACT—Extract Exponent and Sign
Page 293 and 294: FYL2XP1—Compute y ∗ log 2 (x +1
Page 295 and 296: 64-Bit Mode Exceptions#SS(0)If a me
Page 299 and 300: HSUBPD—Horizontal Subtract Packed
Page 301 and 302: HSUBPS—Horizontal Subtract Packed
Page 303 and 304: IDIV—Signed DivideOpcode Instruct
Page 305 and 306: IMUL—Signed MultiplyOpcode Instru
Page 307 and 308: IN—Input from PortOpcode Instruct
Page 311 and 312: Compatibility Mode ExceptionsSame a
Page 313 and 314: Real-Address Mode Exceptions#GPIf a
Page 315 and 316: INVD—Invalidate Internal CachesOp
Page 317 and 318: IRET/IRETD—Interrupt ReturnOpcode
Page 319 and 320: Jcc—Jump if Condition Is MetOpcod
Page 321 and 322: Opcode Instruction 64-Bit Mode Comp
Page 323 and 324: #SS(0)#NP (selector)#PF(fault-code)
Page 325 and 326: LAHF—Load Status Flags into AH Re
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Page 331 and 332: LDS/LES/LFS/LGS/LSS—Load Far Poin
Page 333 and 334: LEA—Load Effective AddressOpcode
Page 335 and 336: LES—Load Full PointerSee entry fo
Page 337 and 338: LFS—Load Full PointerSee entry fo
Page 339 and 340: LGS—Load Full PointerSee entry fo
Page 343 and 344: LMSW—Load Machine Status WordOpco
Page 345 and 346: LODS/LODSB/LODSW/LODSD/LODSQ—Load
Page 347 and 348: LOOP/LOOPcc—Loop According to ECX
Page 349 and 350: LSS—Load Full PointerSee entry fo
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IntelÂ® Extended Memory 64 Technology Software Developer's Guide

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