Intel® Extended Memory 64 Technology Software Developer's Guide

LDMXCSR—Load MXCSR RegisterOpcode Instruction 64-Bit Mode Compat/Leg DescriptionMode0F,AE,/2 LDMXCSR m32 Valid Valid Load MXCSR register from m32.IA-32e Mode OperationSame as legacy mode.C/C++ Compiler Intrinsic Equivalent_mm_setcsr(unsigned int i)Numeric ExceptionsNone.Protected Mode Exceptions#GP(0)#SS(0)#PF(fault-code)#NM#UD#AC(0)For an illegal memory operand effective address in the CS, DS, ES, FS, or GS segments.For an attempt to set reserved bits in MXCSR.For an illegal address in the SS segment.For a page fault.If TS in CR0 is set.If EM in CR0 is set.If OSFXSR in CR4 is 0.If CPUID feature flag SSE is 0.If alignment checking is enabled and an unaligned memory reference is made while thecurrent privilege level is 3.Real Address Mode Exceptions#GP(0)#GP(0)#NM#UDFor an attempt to set reserved bits in MXCSR.If any part of the operand would lie outside of the effective address space from 0 to FFFFH.If TS in CR0 is set.If EM in CR0 is set.If OSFXSR in CR4 is 0.If CPUID feature flag SSE is 0.Virtual 8086 Mode ExceptionsSame exceptions as in Real Address Mode.#PF(fault-code)#AC(0)For a page fault.If alignment checking is enabled and an unaligned memory reference is made.Compatibility Mode ExceptionsSame as for protected mode exceptions.Vol. 1 2-279