IntelÂ® Extended Memory 64 Technology Software Developer's Guide

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#PF(fault-code)#NM#UDFor a page fault.If TS in CR0 is set.If EM in CR0 is set.If OSFXSR in CR4 is 0.If CPUID feature flag SSE2 is 0.2-34 Vol. 1
ANDPS—Bitwise Logical AND of Packed Single-Precision Floating-Point ValuesOpcode Instruction <strong>64</strong>-Bit Mode Compat/Leg DescriptionMode0F 54 /r ANDPS xmm1, xmm2/m128 Valid Valid Bitwise logical AND of xmm2/m128 andxmm1.IA-32e Mode OperationEnables access to XMM8-XMM15.SIMD Floating-Point ExceptionsNone.Protected Mode Exceptions#GP(0)#SS(0)#PF(fault-code)#NM#UDFor an illegal memory operand effective address in the CS, DS, ES, FS or GS segments.If memory operand is not aligned on a 16-byte boundary, regardless of segment.For an illegal address in the SS segment.For a page fault.If TS in CR0 is set.If EM in CR0 is set.If OSFXSR in CR4 is 0.If CPUID feature flag SSE is 0.Real-Address Mode Exceptions#GP(0)#GP(0)#NM#UDIf memory operand is not aligned on a 16-byte boundary, regardless of segment.If any part of the operand lies outside the effective address space from 0 to FFFFH.If TS in CR0 is set.If EM in CR0 is set.If OSFXSR in CR4 is 0.If CPUID feature flag SSE is 0.Virtual-8086 Mode ExceptionsSame exceptions as in Real Address Mode#PF(fault-code)For a page fault.Compatibility Mode ExceptionsSame as protected mode exceptions.<strong>64</strong>-Bit Mode Exceptions#SS(0)#GP(0)If a memory address referencing the SS segment is in a non-canonical form.If the memory address is in a non-canonical form.If memory operand is not aligned on a 16-byte boundary, regardless of segment.Vol. 1 2-35
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Intel ® Extended Memory 64 Technol
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1.6.9.1. Call Gates. . . . . . . .
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FSUB/FSUBP/FISUB—Subtract . . . .
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PADDSB/PADDSW—Add Packed Signed I
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-xii Vol. 1
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ModeIA-32emodeOperatingSystemRequir
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1.3. REGISTER-SET CHANGESThis secti
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Table 1-4 IA32_EFER Bit Description
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IA-32e sub-modeTable 1-8 64-Bit Ext
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REX PREFIX0100WR0BOpcodemod!=11ModR
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1.4.2.4. Direct Memory-Offset MOVsI
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The 64-bit default operation-size e
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1.6.2. Register Settings and IA-32e
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1.6.3.4. Compatibility ModeCompatib
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• When in compatibility mode, FS
Page 34 and 35: Prior to activating IA-32e mode, PA
Page 36 and 37: Table 1-22 through Table 1-24 shows
Page 38 and 39: Table 1-26 Reserved Bit CheckingMod
Page 40 and 41: • Bits 29:21 index into the 512-e
Page 42 and 43: Only 64-bit mode call gates can be
Page 44 and 45: Although the hardware task-switchin
Page 46 and 47: Table 1-39 IA-32e Mode Interrupt an
Page 48 and 49: If the IST index for an interrupt g
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Page 52 and 53: • ib, iw, id, io — A 1-byte (ib
Page 54 and 55: • m16:16, m16:32 & m16:64 —A me
Page 56 and 57: which is either 16, 32 or 64-bits.
Page 58 and 59: 2.1.3.1. IA-32e Mode OperationThe s
Page 60 and 61: 2.1.10. SIMD Floating-Point Excepti
Page 62 and 63: AAD—ASCII Adjust AX Before Divisi
Page 64 and 65: AAS—ASCII Adjust AL After Subtrac
Page 66 and 67: Real-Address Mode Exceptions#GPIf a
Page 70 and 71: 64-Bit Mode Exceptions#SS(0)If a me
Page 86 and 87: #PF(fault-code)#NM#UDFor a page fau
Page 92 and 93: BOUND—Check Array Index Against B
Page 94 and 95: BSF—Bit Scan ForwardOpcode Instru
Page 96 and 97: BSWAP—Byte SwapOpcode Instruction
Page 98 and 99: #AC(0)If alignment checking is enab
Page 100 and 101: #GP(0)#PF(fault-code)#AC(0)If the m
Page 102 and 103: #PF(fault-code)#AC(0)If a page faul
Page 104: 64-Bit Mode Exceptions#SS(0)If a me
Page 107 and 108: Compatibility Mode ExceptionsSame a
Page 109 and 110: CDQ—Convert Double to QuadSee ent
Page 111 and 112: CLD—Clear Direction FlagOpcode In
Page 113 and 114: CLI—Clear Interrupt FlagOpcode In
Page 115 and 116: CMC—Complement Carry FlagOpcode I
Page 117 and 118: Opcode Instruction 64-Bit Mode Comp
Page 119 and 120: CMP—Compare Two OperandsOpcode In
Page 121 and 122: CMPPD—Compare Packed Double-Preci
Page 123 and 124: CMPPS—Compare Packed Single-Preci
Page 125 and 126: CMPS/CMPSB/CMPSW/CMPSD/CMPSQ—Comp
Page 127 and 128: CMPSD—Compare Scalar Double-Preci
Page 129 and 130: CMPSS—Compare Scalar Single-Preci
Page 131 and 132: CMPXCHG—Compare and ExchangeOpcod
Page 133 and 134: CMPXCHG8B/CMPXCHG16B—Compare and
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COMISD—Compare Scalar Ordered Dou
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COMISS—Compare Scalar Ordered Sin
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CPUID—CPU IdentificationOpcode In
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Initial EAXValue80000005H80000006H8
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Table 2-8 CPUID Feature Information
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• The most significant bit (bit 3
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Table 2-10 Brand String Offsets (Co
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CVTDQ2PD—Convert Packed Doublewor
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CVTDQ2PS—Convert Packed Doublewor
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CVTPD2DQ—Convert Packed Double-Pr
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CVTPD2PI—Convert Packed Double-Pr
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CVTPD2PS—Covert Packed Double-Pre
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CVTPI2PD—Convert Packed Doublewor
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CVTPI2PS—Convert Packed Doublewor
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CVTPS2DQ—Convert Packed Single-Pr
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CVTPS2PD—Covert Packed Single-Pre
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CVTPS2PI—Convert Packed Single-Pr
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CVTSD2SI—Convert Scalar Double-Pr
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CVTSD2SS—Convert Scalar Double-Pr
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CVTSI2SD—Convert Doubleword Integ
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CVTSI2SS—Convert Doubleword Integ
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CVTSS2SD—Convert Scalar Single-Pr
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CVTSS2SI—Convert Scalar Single-Pr
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CVTTPD2PI—Convert with Truncation
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CVTTPD2DQ—Convert with Truncation
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CVTTPS2DQ—Convert with Truncation
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CVTTPS2PI—Convert with Truncation
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CVTTSD2SI—Convert with Truncation
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CVTTSS2SI—Convert with Truncation
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CWD/CDQ/CQQ—Convert Word to Doubl
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DAS—Decimal Adjust AL after Subtr
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64-Bit Mode Exceptions#SS(0)If a me
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Virtual-8086 Mode Exceptions#DE If
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ENTER—Make Stack Frame for Proced
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FABS—Absolute ValueOpcode Instruc
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Real-Address Mode Exceptions#GPIf a
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Virtual-8086 Mode Exceptions#GP(0)I
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FCLEX/FNCLEX—Clear ExceptionsOpco
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FCOM/FCOMP/FCOMPP—Compare Floatin
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FCOMI/FCOMIP/ FUCOMI/FUCOMIP—Comp
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FDECSTP—Decrement Stack-Top Point
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FICOM/FICOMP—Compare IntegerOpcod
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FILD—Load IntegerOpcode Instructi
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FINCSTP—Increment Stack-Top Point
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FIST/FISTP—Store IntegerOpcode In
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FISTTP—Store Integer with Truncat
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FLD—Load Floating Point ValueOpco
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FLD1/FLDL2T/FLDL2E/FLDPI/FLDLG2/FLD
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Compatibility Mode ExceptionsSame a
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FPATAN—Partial ArctangentOpcode I
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FPREM1—Partial RemainderOpcode In
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FRNDINT—Round to IntegerOpcode In
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FSIN—SineOpcode Instruction 64-Bi
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FSQRT—Square RootOpcode Instructi
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Protected Mode Exceptions#GP(0)If a
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Protected Mode Exceptions#GP(0)If a
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FUCOM/FUCOMP/FUCOMPP—Unordered Co
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FXAM—ExamineOpcode Instruction 64
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FXRSTOR—Restore x87 FPU, MMX, SSE
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FXSAVE—Save x87 FPU, MMX, SSE, an
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XMM0 throughXMM7XMM registers (128
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Table 2-14 Layout of the 64-bit FXS
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Protected Mode Exceptions#GP(0)For
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FXTRACT—Extract Exponent and Sign
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FYL2XP1—Compute y ∗ log 2 (x +1
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HSUBPD—Horizontal Subtract Packed
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HSUBPS—Horizontal Subtract Packed
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IDIV—Signed DivideOpcode Instruct
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IMUL—Signed MultiplyOpcode Instru
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IN—Input from PortOpcode Instruct
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Compatibility Mode ExceptionsSame a
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INVD—Invalidate Internal CachesOp
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IRET/IRETD—Interrupt ReturnOpcode
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Jcc—Jump if Condition Is MetOpcod
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Opcode Instruction 64-Bit Mode Comp
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#SS(0)#NP (selector)#PF(fault-code)
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LAHF—Load Status Flags into AH Re
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LDDQU—Load Unaligned Double Quadw
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LDMXCSR—Load MXCSR RegisterOpcode
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LDS/LES/LFS/LGS/LSS—Load Far Poin
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LEA—Load Effective AddressOpcode
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LES—Load Full PointerSee entry fo
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LFS—Load Full PointerSee entry fo
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LGS—Load Full PointerSee entry fo
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LMSW—Load Machine Status WordOpco
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LODS/LODSB/LODSW/LODSD/LODSQ—Load
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LOOP/LOOPcc—Loop According to ECX
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LSS—Load Full PointerSee entry fo
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