Intel® Extended Memory 64 Technology Software Developer's Guide

If the IST index for an interrupt gate is not zero, the IST pointer corresponding to the index is loaded into the RSPwhen an interrupt occurs. The new SS selector is forced to null, and the SS selector’s RPL field is set to the new CPL.The old SS, RSP, RFLAGS, CS, and RIP are pushed onto the new stack. Interrupt processing then proceeds as normal.If the IST index is zero, the modified legacy stack-switching mechanism described above is used.1.6.10.6. Task Priority64-bit extensions build on the 15 external interrupt-priority classes defined by the APIC specification. Priority class 1is the lowest and 15 is the highest. How external interrupts are mapped into these priority classes is platform-dependent.Operating systems can use the TPR to temporarily block specific (generally low-priority) interrupts from interruptinga high-priority task. This is done by loading TPR with a value corresponding to the highest-priority interruptthat is to be blocked. For example, loading TPR with a value of 8 (01000B) blocks all interrupts with a priority of 8 orless, while allowing all interrupts with a priority of 9 or more to be recognized. Loading the TPR with 0 enables allexternal interrupts. Loading TPR with 15 (01111B) disables all external interrupts. The TPR is cleared to 0 on reset.Software can read and write the TPR using a MOV CR8 instruction. The new priority level is established when theMOV CR8 instruction completes execution. Software does not need to force serialization after loading TPR.Use of the MOV CRn instruction requires a privilege level of 0. Programs running at privilege level greater than 0cannot read or write the TPR. An attempt to do so results in a general-protection exception, #GP(0).The TPR is abstracted from the interrupt controller (IC), which prioritizes and manages external interrupt delivery tothe processor. The IC can be an external device, such as an APIC or 8259. Typically, the IC provides a priority mechanismsimilar, if not identical to, the TPR. The IC, however, is considered implementation-dependent with the underlyingpriority mechanisms subject to change. The TPR, by contrast, is part of 64-bit architecture. Software can dependon this definition remaining unchanged. Table 1-41 shows the TPR. Only the low four bits are used. The remaining 60bits are reserved and must be written with zeros, failure to do so results in a general-protection exception, #GP(0).Table 1-41 Task Priority Register - CR863:4 3:0ReservedTask Priority Register (TPR)1.6.10.7. CR8 Interactions with APICThe first implementation of Intel EM64T includes a local advanced programmable interrupt controller (APIC) that issimilar to the APIC used with many IA-32 processors. Some aspects of the local APIC affect the operation of the architecturallydefined task priority register (CR8.TPR).Notable CR8 and APIC interactions are:• The processor powers up with the local APIC enabled.• The APIC must be enabled for CR8 to function as the TPR. The interaction between the CR8 and the APIC is thefollowing: Writes to CR8 are reflected into the APIC's Task Priority Register.• APIC.TPR.7:4 = CR8.3:0, APIC.TPR.3:0 = 0. Reads of CR8 return APIC.TPR.7:4, zero is extended to 64 bits.• There are no ordering mechanisms between direct updates of the APIC.TPR and CR8. It is expected thatoperating software will implement either direct APIC TPR updates or CR8 style TPR updates but will not mixthem. Software can use a serializing instruction (e.g. CPUID) to serialize updates between MOV CR8 and storesto the APIC.1-36 Vol. 1