Intel® Extended Memory 64 Technology Software Developer's Guide

FXRSTOR—Restore x87 FPU, MMX, SSE, and SSE2 StateOpcode Instruction 64-Bit Mode Compat/Leg DescriptionMode0F AE /1 FXRSTOR m512byte Valid Valid Restore the x87 FPU, MMX, XMM, and MXCSRregister state from m512byte.x87 FPU and SIMD Floating-Point ExceptionsNone.IA-32e Mode OperationSee FXSAVE for IA-32e Mode save/restore format.Protected Mode Exceptions#GP(0)#SS(0)#MF#PF(fault-code)#NM#UD#ACFor an illegal memory operand effective address in the CS, DS, ES, FS or GS segments.If memory operand is not aligned on a 16-byte boundary, regardless of segment. (See alignmentcheck exception [#AC] below.)If attempting to set a reserved bit in MXCSR.For an illegal address in the SS segment.If there is a pending x87 FPU exception.For a page fault.If TS in CR0 is set.If EM in CR0 is set.If CPUID feature flag FXSR is 0.If instruction is preceded by a LOCK prefix.If this exception is disabled a general protection exception (#GP) is signaled if the memoryoperand is not aligned on a 16-byte boundary, as described above. If the alignment checkexception (#AC) is enabled (and the CPL is 3), signaling of #AC is not guaranteed and mayvary with implementation, as follows. In all implementations where #AC is not signaled, ageneral protection exception is signaled in its place. In addition, the width of the alignmentcheck may also vary with implementation. For instance, for a given implementation, analignment check exception might be signaled for a 2-byte misalignment, whereas a generalprotection exception might be signaled for all other misalignments (4-, 8-, or 16-bytemisalignments).Real-Address Mode Exceptions#GP(0)#GP(0)#NM#MF#UDIf memory operand is not aligned on a 16-byte boundary, regardless of segment.If any part of the operand lies outside the effective address space from 0 to FFFFH.If TS in CR0 is set.If there is a pending x87 FPU exception.If EM in CR0 is set.If CPUID feature flag FXSR is 0.If instruction is preceded by a LOCK override prefix.Vol. 1 2-231