IntelÂ® Extended Memory 64 Technology Software Developer's Guide

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FCMOVcc—Floating-Point Conditional MoveOpcode Instruction 64-Bit Mode Compat/Leg DescriptionModeDA C0+i FCMOVB ST(0), ST(i) Valid Valid Move if below (CF=1)DA C8+i FCMOVE ST(0), ST(i) Valid Valid Move if equal (ZF=1)DA D0+i FCMOVBE ST(0), ST(i) Valid Valid Move if below or equal (CF=1 or ZF=1)DA D8+i FCMOVU ST(0), ST(i) Valid Valid Move if unordered (PF=1)DB C0+i FCMOVNB ST(0), ST(i) Valid Valid Move if not below (CF=0)DB C8+i FCMOVNE ST(0), ST(i) Valid Valid Move if not equal (ZF=0)DB D0+i FCMOVNBE ST(0), ST(i) Valid Valid Move if not below or equal (CF=0 andZF=0)DB D8+i FCMOVNU ST(0), ST(i) Valid Valid Move if not unordered (PF=0)IA-32e Mode OperationSame as legacy mode.FPU Flags AffectedC1Set to 0 if stack underflow occurred.C0, C2, C3 Undefined.Floating-Point Exceptions#ISStack underflow occurred.Integer Flags AffectedNone.Protected Mode Exceptions#NM#MFEM or TS in CR0 is set.If there is a pending x87 FPU exception.Real-Address Mode Exceptions#NM#MFEM or TS in CR0 is set.If there is a pending x87 FPU exception.Virtual-8086 Mode Exceptions#NM#MFEM or TS in CR0 is set.If there is a pending x87 FPU exception.Compatibility Mode ExceptionsSame as for protected mode exceptions.64-Bit Mode ExceptionsSame as for protected mode exceptions.2-170 Vol. 1
FCOM/FCOMP/FCOMPP—Compare Floating Point ValuesOpcode Instruction 64-Bit Mode Compat/Leg DescriptionModeD8 /2 FCOM m32fp Valid Valid Compare ST(0) with m32fp.DC /2 FCOM m64fp Valid Valid Compare ST(0) with m64fp.D8 D0+i FCOM ST(i) Valid Valid Compare ST(0) with ST(i).D8 D1 FCOM Valid Valid Compare ST(0) with ST(1).D8 /3 FCOMP m32fp Valid Valid Compare ST(0) with m32fp and pop registerstack.DC /3 FCOMP m64fp Valid Valid Compare ST(0) with m64fp and pop registerstack.D8 D8+i FCOMP ST(i) Valid Valid Compare ST(0) with ST(i) and pop registerstack.D8 D9 FCOMP Valid Valid Compare ST(0) with ST(1) and pop registerstack.DE D9 FCOMPP Valid Valid Compare ST(0) with ST(1) and pop registerstack twice.IA-32e Mode OperationSame as legacy mode.FPU Flags AffectedC1 Cleared to 0.C0, C2, C3 See table below.Condition C3 C2 C0ST(0) > SRC 0 0 0ST(0) < SRC 0 0 1ST(0) = SRC 1 0 0Unordered* 1 1 1Floating-Point Exceptions#ISStack underflow occurred.#IAOne or both operands are NaN values or have unsupported formats.Register is marked empty.#D One or both operands are denormal values.Vol. 1 2-171
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Intel ® Extended Memory 64 Technol
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1.6.9.1. Call Gates. . . . . . . .
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FSUB/FSUBP/FISUB—Subtract . . . .
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PADDSB/PADDSW—Add Packed Signed I
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-xii Vol. 1
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ModeIA-32emodeOperatingSystemRequir
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1.3. REGISTER-SET CHANGESThis secti
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Table 1-4 IA32_EFER Bit Description
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IA-32e sub-modeTable 1-8 64-Bit Ext
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REX PREFIX0100WR0BOpcodemod!=11ModR
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1.4.2.4. Direct Memory-Offset MOVsI
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The 64-bit default operation-size e
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1.6.2. Register Settings and IA-32e
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1.6.3.4. Compatibility ModeCompatib
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• When in compatibility mode, FS
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Prior to activating IA-32e mode, PA
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Table 1-22 through Table 1-24 shows
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Table 1-26 Reserved Bit CheckingMod
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• Bits 29:21 index into the 512-e
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Only 64-bit mode call gates can be
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Although the hardware task-switchin
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Table 1-39 IA-32e Mode Interrupt an
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If the IST index for an interrupt g
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1-38 Vol. 1
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• ib, iw, id, io — A 1-byte (ib
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• m16:16, m16:32 & m16:64 —A me
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which is either 16, 32 or 64-bits.
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2.1.3.1. IA-32e Mode OperationThe s
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2.1.10. SIMD Floating-Point Excepti
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AAD—ASCII Adjust AX Before Divisi
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AAS—ASCII Adjust AL After Subtrac
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Real-Address Mode Exceptions#GPIf a
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64-Bit Mode Exceptions#SS(0)If a me
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#PF(fault-code)#NM#UDFor a page fau
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BOUND—Check Array Index Against B
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BSF—Bit Scan ForwardOpcode Instru
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BSWAP—Byte SwapOpcode Instruction
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#AC(0)If alignment checking is enab
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#GP(0)#PF(fault-code)#AC(0)If the m
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#PF(fault-code)#AC(0)If a page faul
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Compatibility Mode ExceptionsSame a
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CDQ—Convert Double to QuadSee ent
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CLD—Clear Direction FlagOpcode In
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CLI—Clear Interrupt FlagOpcode In
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CMC—Complement Carry FlagOpcode I
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Opcode Instruction 64-Bit Mode Comp
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CMP—Compare Two OperandsOpcode In
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CMPPD—Compare Packed Double-Preci
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CMPPS—Compare Packed Single-Preci
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CMPS/CMPSB/CMPSW/CMPSD/CMPSQ—Comp
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CMPSD—Compare Scalar Double-Preci
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CMPSS—Compare Scalar Single-Preci
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CMPXCHG—Compare and ExchangeOpcod
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CMPXCHG8B/CMPXCHG16B—Compare and
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COMISD—Compare Scalar Ordered Dou
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COMISS—Compare Scalar Ordered Sin
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CPUID—CPU IdentificationOpcode In
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Initial EAXValue80000005H80000006H8
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Table 2-8 CPUID Feature Information
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• The most significant bit (bit 3
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Table 2-10 Brand String Offsets (Co
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CVTDQ2PD—Convert Packed Doublewor
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CVTDQ2PS—Convert Packed Doublewor
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CVTPD2DQ—Convert Packed Double-Pr
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CVTPD2PI—Convert Packed Double-Pr
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CVTPD2PS—Covert Packed Double-Pre
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CVTPI2PD—Convert Packed Doublewor
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CVTPI2PS—Convert Packed Doublewor
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CVTPS2DQ—Convert Packed Single-Pr
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CVTPS2PD—Covert Packed Single-Pre
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CVTPS2PI—Convert Packed Single-Pr
Page 169 and 170: CVTSD2SI—Convert Scalar Double-Pr
Page 171 and 172: CVTSD2SS—Convert Scalar Double-Pr
Page 173 and 174: CVTSI2SD—Convert Doubleword Integ
Page 175 and 176: CVTSI2SS—Convert Doubleword Integ
Page 177 and 178: CVTSS2SD—Convert Scalar Single-Pr
Page 179 and 180: CVTSS2SI—Convert Scalar Single-Pr
Page 181 and 182: CVTTPD2PI—Convert with Truncation
Page 183 and 184: CVTTPD2DQ—Convert with Truncation
Page 185 and 186: CVTTPS2DQ—Convert with Truncation
Page 187 and 188: CVTTPS2PI—Convert with Truncation
Page 189 and 190: CVTTSD2SI—Convert with Truncation
Page 191 and 192: CVTTSS2SI—Convert with Truncation
Page 193 and 194: CWD/CDQ/CQQ—Convert Word to Doubl
Page 195 and 196: DAS—Decimal Adjust AL after Subtr
Page 197 and 198: 64-Bit Mode Exceptions#SS(0)If a me
Page 199 and 200: Virtual-8086 Mode Exceptions#DE If
Page 209 and 210: ENTER—Make Stack Frame for Proced
Page 211 and 212: FABS—Absolute ValueOpcode Instruc
Page 213 and 214: Real-Address Mode Exceptions#GPIf a
Page 217 and 218: Virtual-8086 Mode Exceptions#GP(0)I
Page 219: FCLEX/FNCLEX—Clear ExceptionsOpco
Page 223 and 224: FCOMI/FCOMIP/ FUCOMI/FUCOMIP—Comp
Page 225 and 226: FDECSTP—Decrement Stack-Top Point
Page 231 and 232: FICOM/FICOMP—Compare IntegerOpcod
Page 233 and 234: FILD—Load IntegerOpcode Instructi
Page 235 and 236: FINCSTP—Increment Stack-Top Point
Page 237 and 238: FIST/FISTP—Store IntegerOpcode In
Page 239 and 240: FISTTP—Store Integer with Truncat
Page 241 and 242: FLD—Load Floating Point ValueOpco
Page 243 and 244: FLD1/FLDL2T/FLDL2E/FLDPI/FLDLG2/FLD
Page 247 and 248: Compatibility Mode ExceptionsSame a
Page 251 and 252: FPATAN—Partial ArctangentOpcode I
Page 253 and 254: FPREM1—Partial RemainderOpcode In
Page 255 and 256: FRNDINT—Round to IntegerOpcode In
Page 261 and 262: FSIN—SineOpcode Instruction 64-Bi
Page 263 and 264: FSQRT—Square RootOpcode Instructi
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Virtual-8086 Mode Exceptions#GP(0)I
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Protected Mode Exceptions#GP(0)If a
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Protected Mode Exceptions#GP(0)If a
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FUCOM/FUCOMP/FUCOMPP—Unordered Co
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FXAM—ExamineOpcode Instruction 64
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FXRSTOR—Restore x87 FPU, MMX, SSE
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FXSAVE—Save x87 FPU, MMX, SSE, an
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XMM0 throughXMM7XMM registers (128
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Table 2-14 Layout of the 64-bit FXS
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Protected Mode Exceptions#GP(0)For
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FXTRACT—Extract Exponent and Sign
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FYL2XP1—Compute y ∗ log 2 (x +1
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HSUBPD—Horizontal Subtract Packed
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HSUBPS—Horizontal Subtract Packed
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IDIV—Signed DivideOpcode Instruct
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IMUL—Signed MultiplyOpcode Instru
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IN—Input from PortOpcode Instruct
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Compatibility Mode ExceptionsSame a
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INVD—Invalidate Internal CachesOp
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IRET/IRETD—Interrupt ReturnOpcode
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Jcc—Jump if Condition Is MetOpcod
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Opcode Instruction 64-Bit Mode Comp
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#SS(0)#NP (selector)#PF(fault-code)
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LAHF—Load Status Flags into AH Re
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LDDQU—Load Unaligned Double Quadw
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LDMXCSR—Load MXCSR RegisterOpcode
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LDS/LES/LFS/LGS/LSS—Load Far Poin
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LEA—Load Effective AddressOpcode
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LES—Load Full PointerSee entry fo
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LFS—Load Full PointerSee entry fo
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LGS—Load Full PointerSee entry fo
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LMSW—Load Machine Status WordOpco
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LODS/LODSB/LODSW/LODSD/LODSQ—Load
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LOOP/LOOPcc—Loop According to ECX
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LSS—Load Full PointerSee entry fo
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