Intel® Extended Memory 64 Technology Software Developer's Guide

ADDPD—Add Packed Double-Precision Floating-Point ValuesOpcode Instruction 64-Bit Mode Compat/Leg DescriptionMode66 0F 58 /r ADDPD xmm1, xmm2/m128 Valid Valid Add packed double-precision floatingpointvalues from xmm2/m128 to xmm1.IA-32e Mode OperationEnables access to XMM8-XMM15 registers.SIMD Floating-Point ExceptionsOverflow, Underflow, Invalid, Precision, Denormal.Protected Mode Exceptions#GP(0)For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments.If memory operand is not aligned on a 16-byte boundary, regardless of segment.#SS(0)For an illegal address in the SS segment.#PF(fault-code) For a page fault.#NMIf TS in CR0 is set.#XM If an unmasked SIMD floating-point exception and OSXMMEXCPT in CR4 is 1.#UD If an unmasked SIMD floating-point exception and OSXMMEXCPT in CR4 is 0.If EM in CR0 is set.If OSFXSR in CR4 is 0.If CPUID feature flag SSE2 is 0.Real-Address Mode Exceptions#GP(0)If memory operand is not aligned on a 16-byte boundary, regardless of segment.#GP(0)If any part of the operand lies outside the effective address space from 0 to FFFFH.#NMIf TS in CR0 is set.#XM If an unmasked SIMD floating-point exception and OSXMMEXCPT in CR4 is 1.#UD If an unmasked SIMD floating-point exception and OSXMMEXCPT in CR4 is 0.If EM in CR0 is set.If OSFXSR in CR4 is 0.If CPUID feature flag SSE2 is 0.Virtual-8086 Mode ExceptionsSame exceptions as in Real Address Mode#PF(fault-code)For a page faultCompatibility Mode ExceptionsSame as protected mode exceptions.Vol. 1 2-19