IntelÂ® Extended Memory 64 Technology Software Developer's Guide

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REX PREFIX0100WR0BOpcodemod!=11ModRM Byteregrrrr/mbbbRrrrBbbbFigure 1-2. Memory Addressing Without a SIB Byte, REX.X is Not Used, ModRM Reg Field!REX PREFIX0100WR0BOpcodemod11ModRM Byteregrrrr/mbbbRrrrBbbbFigure 1-3. Register-Register Addressing (No Memory Operand), REX.X is Not UsedREX PREFIX0100WRXBOpcodemod!=11ModRM Byteregrrrr/m100scalessSIB ByteindexxxxbasebbbRrrrFigure 1-4. Memory Addressing With a SIB ByteXxxxBbbb1-10 Vol. 1
REX PREFIX0100W00BOpcoderegbbbBbbbFigure 1-5. Register Operand Coded in Opcode Byte, REX.X and REX.R Are Not UsedIn the legacy IA-32 architecture, byte registers (AH, AL, BH, BL, CH, CL, DH, and DL) are encoded in the ModRMbyte’s reg field, the r/m field or the opcode reg field as registers 0 through 7. The REX prefixes provide an additionaladdressing capability to byte-registers that makes the least-significant byte of GPRs available for byte operations.Certain combinations of the fields of the ModRM byte and the SIB byte have special meaning for register encodings.For some combinations, instruction fields expanded by the REX prefix are not decoded. Table 1-10 describes how eachcase behaves.ModRM or SIB Sub-field Encodings Compatibility ModeOperationTable 1-10 Special Cases of REX EncodingsCompatibility ModeImplicationsModRM Byte mod != 11 SIB byte present. SIB byte required forr/m == b*100(ESP)ESP-based addressingModRM Byte mod == 0 Base register notr/m == b*101(EBP)usedSIB Byte index == 0100(ESP) Index register notusedSIB Byte base == 0101(EBP) Base register isunused ifmod = 0* Don’t care about the value of b (REX.B).EBP without adisplacement must bedone usingmod = 01 withdisplacement of 0ESP cannot be used asan index registerBase register dependson mod encodingAdditional ImplicationsREX prefix adds a fourth bit (b)which is not decoded (don't care)SIB byte also required for R12-based addressingREX prefix adds a fourth bit (b)which is not decoded (don't care)Using RBP or R13 withoutdisplacement must be done usingmod = 01 with a displacement of 0REX prefix adds a fourth bit (b)which is decoded.There are no additionalimplications. The expanded indexfield allows distinguishing RSPfrom R12, therefore R12 can beused as an index.REX prefix adds a fourth bit (b)which is decoded.There are no additionalimplications. The expanded basefield is used to distinguish RBPfrom R13, allowing R13 to be usedas a SIB base regardless of themod.1.4.2.3. DisplacementAddressing in 64-bit mode uses existing 32-bit ModRM and SIB encodings. In particular, the ModRM and SIBdisplacement sizes do not change. They remain 8 bits or 32 bits and are sign-extended to 64 bits.Vol. 1 1-11
Page 1 and 2: Intel ® Extended Memory 64 Technol
Page 4 and 5: 1.6.9.1. Call Gates. . . . . . . .
Page 7 and 8: FSUB/FSUBP/FISUB—Subtract . . . .
Page 9 and 10: PADDSB/PADDSW—Add Packed Signed I
Page 12 and 13: -xii Vol. 1
Page 14 and 15: ModeIA-32emodeOperatingSystemRequir
Page 16 and 17: 1.3. REGISTER-SET CHANGESThis secti
Page 18 and 19: Table 1-4 IA32_EFER Bit Description
Page 20 and 21: IA-32e sub-modeTable 1-8 64-Bit Ext
Page 24 and 25: 1.4.2.4. Direct Memory-Offset MOVsI
Page 26 and 27: The 64-bit default operation-size e
Page 28 and 29: 1.6.2. Register Settings and IA-32e
Page 30 and 31: 1.6.3.4. Compatibility ModeCompatib
Page 32 and 33: • When in compatibility mode, FS
Page 34 and 35: Prior to activating IA-32e mode, PA
Page 36 and 37: Table 1-22 through Table 1-24 shows
Page 38 and 39: Table 1-26 Reserved Bit CheckingMod
Page 40 and 41: • Bits 29:21 index into the 512-e
Page 42 and 43: Only 64-bit mode call gates can be
Page 44 and 45: Although the hardware task-switchin
Page 46 and 47: Table 1-39 IA-32e Mode Interrupt an
Page 48 and 49: If the IST index for an interrupt g
Page 50 and 51: 1-38 Vol. 1
Page 52 and 53: • ib, iw, id, io — A 1-byte (ib
Page 54 and 55: • m16:16, m16:32 & m16:64 —A me
Page 56 and 57: which is either 16, 32 or 64-bits.
Page 58 and 59: 2.1.3.1. IA-32e Mode OperationThe s
Page 60 and 61: 2.1.10. SIMD Floating-Point Excepti
Page 62 and 63: AAD—ASCII Adjust AX Before Divisi
Page 64 and 65: AAS—ASCII Adjust AL After Subtrac
Page 66 and 67: Real-Address Mode Exceptions#GPIf a
Page 68 and 69: Real-Address Mode Exceptions#GPIf a
Page 70 and 71: 64-Bit Mode Exceptions#SS(0)If a me
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64-Bit Mode Exceptions#SS(0)If a me
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Real-Address Mode Exceptions#GPIf a
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#PF(fault-code)#NM#UDFor a page fau
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BOUND—Check Array Index Against B
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BSF—Bit Scan ForwardOpcode Instru
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BSWAP—Byte SwapOpcode Instruction
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#AC(0)If alignment checking is enab
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#GP(0)#PF(fault-code)#AC(0)If the m
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#PF(fault-code)#AC(0)If a page faul
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Compatibility Mode ExceptionsSame a
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CDQ—Convert Double to QuadSee ent
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CLD—Clear Direction FlagOpcode In
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CLI—Clear Interrupt FlagOpcode In
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CMC—Complement Carry FlagOpcode I
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Opcode Instruction 64-Bit Mode Comp
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CMP—Compare Two OperandsOpcode In
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CMPPD—Compare Packed Double-Preci
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CMPPS—Compare Packed Single-Preci
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CMPS/CMPSB/CMPSW/CMPSD/CMPSQ—Comp
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CMPSD—Compare Scalar Double-Preci
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CMPSS—Compare Scalar Single-Preci
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CMPXCHG—Compare and ExchangeOpcod
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CMPXCHG8B/CMPXCHG16B—Compare and
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COMISD—Compare Scalar Ordered Dou
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COMISS—Compare Scalar Ordered Sin
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CPUID—CPU IdentificationOpcode In
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Initial EAXValue80000005H80000006H8
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Table 2-8 CPUID Feature Information
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• The most significant bit (bit 3
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Table 2-10 Brand String Offsets (Co
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CVTDQ2PD—Convert Packed Doublewor
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CVTDQ2PS—Convert Packed Doublewor
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CVTPD2DQ—Convert Packed Double-Pr
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CVTPD2PI—Convert Packed Double-Pr
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CVTPD2PS—Covert Packed Double-Pre
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CVTPI2PD—Convert Packed Doublewor
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CVTPI2PS—Convert Packed Doublewor
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CVTPS2DQ—Convert Packed Single-Pr
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CVTPS2PD—Covert Packed Single-Pre
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CVTPS2PI—Convert Packed Single-Pr
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CVTSD2SI—Convert Scalar Double-Pr
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CVTSD2SS—Convert Scalar Double-Pr
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CVTSI2SD—Convert Doubleword Integ
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CVTSI2SS—Convert Doubleword Integ
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CVTSS2SD—Convert Scalar Single-Pr
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CVTSS2SI—Convert Scalar Single-Pr
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CVTTPD2PI—Convert with Truncation
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CVTTPD2DQ—Convert with Truncation
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CVTTPS2DQ—Convert with Truncation
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CVTTPS2PI—Convert with Truncation
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CVTTSD2SI—Convert with Truncation
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CVTTSS2SI—Convert with Truncation
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CWD/CDQ/CQQ—Convert Word to Doubl
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DAS—Decimal Adjust AL after Subtr
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Virtual-8086 Mode Exceptions#DE If
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ENTER—Make Stack Frame for Proced
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FABS—Absolute ValueOpcode Instruc
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Virtual-8086 Mode Exceptions#GP(0)I
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FCLEX/FNCLEX—Clear ExceptionsOpco
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FCOM/FCOMP/FCOMPP—Compare Floatin
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FCOMI/FCOMIP/ FUCOMI/FUCOMIP—Comp
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FDECSTP—Decrement Stack-Top Point
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FICOM/FICOMP—Compare IntegerOpcod
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FILD—Load IntegerOpcode Instructi
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FINCSTP—Increment Stack-Top Point
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FIST/FISTP—Store IntegerOpcode In
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FISTTP—Store Integer with Truncat
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FLD—Load Floating Point ValueOpco
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FLD1/FLDL2T/FLDL2E/FLDPI/FLDLG2/FLD
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FPATAN—Partial ArctangentOpcode I
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FPREM1—Partial RemainderOpcode In
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FRNDINT—Round to IntegerOpcode In
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FSIN—SineOpcode Instruction 64-Bi
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FSQRT—Square RootOpcode Instructi
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Protected Mode Exceptions#GP(0)If a
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Protected Mode Exceptions#GP(0)If a
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FUCOM/FUCOMP/FUCOMPP—Unordered Co
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FXAM—ExamineOpcode Instruction 64
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FXRSTOR—Restore x87 FPU, MMX, SSE
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FXSAVE—Save x87 FPU, MMX, SSE, an
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XMM0 throughXMM7XMM registers (128
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Table 2-14 Layout of the 64-bit FXS
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Protected Mode Exceptions#GP(0)For
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FXTRACT—Extract Exponent and Sign
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FYL2XP1—Compute y ∗ log 2 (x +1
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HSUBPD—Horizontal Subtract Packed
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HSUBPS—Horizontal Subtract Packed
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IDIV—Signed DivideOpcode Instruct
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IMUL—Signed MultiplyOpcode Instru
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IN—Input from PortOpcode Instruct
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INVD—Invalidate Internal CachesOp
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IRET/IRETD—Interrupt ReturnOpcode
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Jcc—Jump if Condition Is MetOpcod
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Opcode Instruction 64-Bit Mode Comp
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#SS(0)#NP (selector)#PF(fault-code)
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LAHF—Load Status Flags into AH Re
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LDDQU—Load Unaligned Double Quadw
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LDMXCSR—Load MXCSR RegisterOpcode
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LDS/LES/LFS/LGS/LSS—Load Far Poin
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LEA—Load Effective AddressOpcode
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LES—Load Full PointerSee entry fo
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LFS—Load Full PointerSee entry fo
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LGS—Load Full PointerSee entry fo
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LMSW—Load Machine Status WordOpco
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LODS/LODSB/LODSW/LODSD/LODSQ—Load
Page 347 and 348:
LOOP/LOOPcc—Loop According to ECX
Page 349 and 350:
LSS—Load Full PointerSee entry fo
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