IntelÂ® Extended Memory 64 Technology Software Developer's Guide

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Virtual-8086 Mode Exceptions#GP(0)If the return instruction pointer is not within the return code segment limit.IF IOPL not equal to 3#PF(fault-code) If a page fault occurs.#SS(0)If the top bytes of stack are not within stack limits.#AC(0)If an unaligned memory reference occurs and alignment checking is enabled.#GP(0)The INVLPG instruction cannot be executed at the virtual-8086 mode.Compatibility Mode ExceptionsSame as for protected mode exceptions.64-Bit Mode Exceptions#GP(0)If the EFLAGS.NT bit is set.If the return code segment selector is null.If the stack segment selector is null going back to compatibility mode.If the stack segment selector is null going back to CPL3 64-bit mode.If a null stack segment selector RPL is not equal to CPL going back to non-CPL3 64-bitmode.If the return instruction pointer is not within the return code segment limit.If the return instruction pointer is non-canonical.#GP(Selector) If a segment selector index is outside its descriptor table limits.If a segment descriptor memory address is non-canonical.If the segment descriptor for a code segment does not indicate it is a code segment.If the proposed new code segment descriptor has both the D-bit and L-bit set.If the DPL for a nonconforming-code segment is not equal to the RPL of the code segmentselector.If CPL is greater than the RPL of the code segment selector.If the DPL of a conforming-code segment is greater than the return code segment selectorRPL.If the stack segment is not a writable data segment.If the stack segment descriptor DPL is not equal to the RPL of the return code segmentselector.If the stack segment selector RPL is not equal to the RPL of the return code segmentselector.#SS(0)If an attempt to pop a value off the stack violates the SS limit.If an attempt to pop a value off the stack causes a non-canonical address to be referenced.#NP(selector)If the return code or stack segment is not present.#PF(fault-code) If a page fault occurs.#AC(0)If an unaligned memory reference occurs when the CPL is 3 and alignment checking isenabled.2-268 Vol. 1
Jcc—Jump if Condition Is MetOpcode Instruction 64-Bit Mode Compat/Leg DescriptionMode77 cb JA rel8 Valid Valid Jump short if above (CF=0 and ZF=0)73 cb JAE rel8 Valid Valid Jump short if above or equal (CF=0)72 cb JB rel8 Valid Valid Jump short if below (CF=1)76 cb JBE rel8 Valid Valid Jump short if below or equal (CF=1 or ZF=1)72 cb JC rel8 Valid Valid Jump short if carry (CF=1)E3 cb JCXZ rel8 Valid Valid Jump short if CX register is 0E3 cb JECXZ rel8 Valid Valid Jump short if ECX register is 074 cb JE rel8 Valid Valid Jump short if equal (ZF=1)7F cb JG rel8 Valid Valid Jump short if greater (ZF=0 and SF=OF)7D cb JGE rel8 Valid Valid Jump short if greater or equal (SF=OF)7C cb JL rel8 Valid Valid Jump short if less (SFOF)7E cb JLE rel8 Valid Valid Jump short if less or equal (ZF=1 or SFOF)76 cb JNA rel8 Valid Valid Jump short if not above (CF=1 or ZF=1)72 cb JNAE rel8 Valid Valid Jump short if not above or equal (CF=1)73 cb JNB rel8 Valid Valid Jump short if not below (CF=0)77 cb JNBE rel8 Valid Valid Jump short if not below or equal (CF=0 andZF=0)73 cb JNC rel8 Valid Valid Jump short if not carry (CF=0)75 cb JNE rel8 Valid Valid Jump short if not equal (ZF=0)7E cb JNG rel8 Valid Valid Jump short if not greater (ZF=1 or SFOF)7C cb JNGE rel8 Valid Valid Jump short if not greater or equal (SFOF)7D cb JNL rel8 Valid Valid Jump short if not less (SF=OF)7F cb JNLE rel8 Valid Valid Jump short if not less or equal (ZF=0 andSF=OF)71 cb JNO rel8 Valid Valid Jump short if not overflow (OF=0)7B cb JNP rel8 Valid Valid Jump short if not parity (PF=0)79 cb JNS rel8 Valid Valid Jump short if not sign (SF=0)75 cb JNZ rel8 Valid Valid Jump short if not zero (ZF=0)70 cb JO rel8 Valid Valid Jump short if overflow (OF=1)7A cb JP rel8 Valid Valid Jump short if parity (PF=1)7A cb JPE rel8 Valid Valid Jump short if parity even (PF=1)7B cb JPO rel8 Valid Valid Jump short if parity odd (PF=0)78 cb JS rel8 Valid Valid Jump short if sign (SF=1)74 cb JZ rel8 Valid Valid Jump short if zero (ZF ← 1)0F 87 cw JA rel16 N.S. Valid Jump near if above (CF=0 and ZF=0). Notsupported in 64-bit mode.0F 87 cd JA rel32 Valid Valid Jump near if above (CF=0 and ZF=0)0F 83 cw JAE rel16 N.S. Valid Jump near if above or equal (CF=0). Notsupported in 64-bit mode.0F 83 cd JAE rel32 Valid Valid Jump near if above or equal (CF=0)0F 82 cw JB rel16 N.S. Valid Jump near if below (CF=1). Not supported in 64-bit mode.0F 82 cd JB rel32 Valid Valid Jump near if below (CF=1)0F 86 cw JBE rel16 N.S. Valid Jump near if below or equal (CF=1 or ZF=1).Not supported in 64-bit mode.0F 86 cd JBE rel32 Valid Valid Jump near if below or equal (CF=1 or ZF=1)0F 82 cw JC rel16 N.S. Valid Jump near if carry (CF=1). Not supported in 64-bit mode.0F 82 cd JC rel32 Valid Valid Jump near if carry (CF=1)0F 84 cw JE rel16 N.S. Valid Jump near if equal (ZF=1). Not supported in 64-bit mode.Vol. 1 2-269
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Intel ® Extended Memory 64 Technol
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1.6.9.1. Call Gates. . . . . . . .
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FSUB/FSUBP/FISUB—Subtract . . . .
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PADDSB/PADDSW—Add Packed Signed I
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-xii Vol. 1
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ModeIA-32emodeOperatingSystemRequir
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1.3. REGISTER-SET CHANGESThis secti
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Table 1-4 IA32_EFER Bit Description
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IA-32e sub-modeTable 1-8 64-Bit Ext
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REX PREFIX0100WR0BOpcodemod!=11ModR
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1.4.2.4. Direct Memory-Offset MOVsI
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The 64-bit default operation-size e
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1.6.2. Register Settings and IA-32e
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1.6.3.4. Compatibility ModeCompatib
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• When in compatibility mode, FS
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Prior to activating IA-32e mode, PA
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Table 1-22 through Table 1-24 shows
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Table 1-26 Reserved Bit CheckingMod
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• Bits 29:21 index into the 512-e
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Only 64-bit mode call gates can be
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Although the hardware task-switchin
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Table 1-39 IA-32e Mode Interrupt an
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If the IST index for an interrupt g
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1-38 Vol. 1
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• ib, iw, id, io — A 1-byte (ib
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• m16:16, m16:32 & m16:64 —A me
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which is either 16, 32 or 64-bits.
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2.1.3.1. IA-32e Mode OperationThe s
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2.1.10. SIMD Floating-Point Excepti
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AAD—ASCII Adjust AX Before Divisi
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AAS—ASCII Adjust AL After Subtrac
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Real-Address Mode Exceptions#GPIf a
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64-Bit Mode Exceptions#SS(0)If a me
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#PF(fault-code)#NM#UDFor a page fau
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BOUND—Check Array Index Against B
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BSF—Bit Scan ForwardOpcode Instru
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BSWAP—Byte SwapOpcode Instruction
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#AC(0)If alignment checking is enab
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#GP(0)#PF(fault-code)#AC(0)If the m
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#PF(fault-code)#AC(0)If a page faul
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Compatibility Mode ExceptionsSame a
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CDQ—Convert Double to QuadSee ent
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CLD—Clear Direction FlagOpcode In
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CLI—Clear Interrupt FlagOpcode In
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CMC—Complement Carry FlagOpcode I
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Opcode Instruction 64-Bit Mode Comp
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CMP—Compare Two OperandsOpcode In
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CMPPD—Compare Packed Double-Preci
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CMPPS—Compare Packed Single-Preci
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CMPS/CMPSB/CMPSW/CMPSD/CMPSQ—Comp
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CMPSD—Compare Scalar Double-Preci
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CMPSS—Compare Scalar Single-Preci
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CMPXCHG—Compare and ExchangeOpcod
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CMPXCHG8B/CMPXCHG16B—Compare and
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COMISD—Compare Scalar Ordered Dou
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COMISS—Compare Scalar Ordered Sin
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CPUID—CPU IdentificationOpcode In
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Initial EAXValue80000005H80000006H8
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Table 2-8 CPUID Feature Information
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• The most significant bit (bit 3
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Table 2-10 Brand String Offsets (Co
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CVTDQ2PD—Convert Packed Doublewor
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CVTDQ2PS—Convert Packed Doublewor
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CVTPD2DQ—Convert Packed Double-Pr
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CVTPD2PI—Convert Packed Double-Pr
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CVTPD2PS—Covert Packed Double-Pre
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CVTPI2PD—Convert Packed Doublewor
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CVTPI2PS—Convert Packed Doublewor
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CVTPS2DQ—Convert Packed Single-Pr
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CVTPS2PD—Covert Packed Single-Pre
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CVTPS2PI—Convert Packed Single-Pr
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CVTSD2SI—Convert Scalar Double-Pr
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CVTSD2SS—Convert Scalar Double-Pr
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CVTSI2SD—Convert Doubleword Integ
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CVTSI2SS—Convert Doubleword Integ
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CVTSS2SD—Convert Scalar Single-Pr
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CVTSS2SI—Convert Scalar Single-Pr
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CVTTPD2PI—Convert with Truncation
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CVTTPD2DQ—Convert with Truncation
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CVTTPS2DQ—Convert with Truncation
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CVTTPS2PI—Convert with Truncation
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CVTTSD2SI—Convert with Truncation
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CVTTSS2SI—Convert with Truncation
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CWD/CDQ/CQQ—Convert Word to Doubl
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DAS—Decimal Adjust AL after Subtr
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Virtual-8086 Mode Exceptions#DE If
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ENTER—Make Stack Frame for Proced
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FABS—Absolute ValueOpcode Instruc
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Virtual-8086 Mode Exceptions#GP(0)I
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FCLEX/FNCLEX—Clear ExceptionsOpco
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FCOM/FCOMP/FCOMPP—Compare Floatin
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FCOMI/FCOMIP/ FUCOMI/FUCOMIP—Comp
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FDECSTP—Decrement Stack-Top Point
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FICOM/FICOMP—Compare IntegerOpcod
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FILD—Load IntegerOpcode Instructi
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FINCSTP—Increment Stack-Top Point
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FIST/FISTP—Store IntegerOpcode In
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FISTTP—Store Integer with Truncat
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FLD—Load Floating Point ValueOpco
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FLD1/FLDL2T/FLDL2E/FLDPI/FLDLG2/FLD
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Compatibility Mode ExceptionsSame a
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FPATAN—Partial ArctangentOpcode I
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FPREM1—Partial RemainderOpcode In
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FRNDINT—Round to IntegerOpcode In
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Virtual-8086 Mode Exceptions#GP(0)I
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FSIN—SineOpcode Instruction 64-Bi
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FSQRT—Square RootOpcode Instructi
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Page 267 and 268: Virtual-8086 Mode Exceptions#GP(0)I
Page 273 and 274: Protected Mode Exceptions#GP(0)If a
Page 275 and 276: Protected Mode Exceptions#GP(0)If a
Page 277 and 278: FUCOM/FUCOMP/FUCOMPP—Unordered Co
Page 279 and 280: FXAM—ExamineOpcode Instruction 64
Page 281 and 282: FXRSTOR—Restore x87 FPU, MMX, SSE
Page 283 and 284: FXSAVE—Save x87 FPU, MMX, SSE, an
Page 285 and 286: XMM0 throughXMM7XMM registers (128
Page 287 and 288: Table 2-14 Layout of the 64-bit FXS
Page 289 and 290: Protected Mode Exceptions#GP(0)For
Page 291 and 292: FXTRACT—Extract Exponent and Sign
Page 293 and 294: FYL2XP1—Compute y ∗ log 2 (x +1
Page 295 and 296: 64-Bit Mode Exceptions#SS(0)If a me
Page 299 and 300: HSUBPD—Horizontal Subtract Packed
Page 301 and 302: HSUBPS—Horizontal Subtract Packed
Page 303 and 304: IDIV—Signed DivideOpcode Instruct
Page 305 and 306: IMUL—Signed MultiplyOpcode Instru
Page 307 and 308: IN—Input from PortOpcode Instruct
Page 311 and 312: Compatibility Mode ExceptionsSame a
Page 313 and 314: Real-Address Mode Exceptions#GPIf a
Page 315 and 316: INVD—Invalidate Internal CachesOp
Page 317: IRET/IRETD—Interrupt ReturnOpcode
Page 321 and 322: Opcode Instruction 64-Bit Mode Comp
Page 323 and 324: #SS(0)#NP (selector)#PF(fault-code)
Page 325 and 326: LAHF—Load Status Flags into AH Re
Page 327 and 328: LDDQU—Load Unaligned Double Quadw
Page 329 and 330: LDMXCSR—Load MXCSR RegisterOpcode
Page 331 and 332: LDS/LES/LFS/LGS/LSS—Load Far Poin
Page 333 and 334: LEA—Load Effective AddressOpcode
Page 335 and 336: LES—Load Full PointerSee entry fo
Page 337 and 338: LFS—Load Full PointerSee entry fo
Page 339 and 340: LGS—Load Full PointerSee entry fo
Page 343 and 344: LMSW—Load Machine Status WordOpco
Page 345 and 346: LODS/LODSB/LODSW/LODSD/LODSQ—Load
Page 347 and 348: LOOP/LOOPcc—Loop According to ECX
Page 349 and 350: LSS—Load Full PointerSee entry fo
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IntelÂ® Extended Memory 64 Technology Software Developer's Guide

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