Intel® Extended Memory 64 Technology Software Developer's Guide

FLDCW—Load x87 FPU Control WordOpcode Instruction 64-Bit Mode Compat/Leg DescriptionModeD9 /5 FLDCW m2byte Valid Valid Load FPU control word from m2byte.IA-32e Mode OperationSame as legacy mode.FPU Flags AffectedC0, C1, C2, C3 undefined.Floating-Point ExceptionsNone; however, this operation might unmask a pending exception in the FPU status word. That exception is then generatedupon execution of the next “waiting” floating-point instruction.Protected Mode Exceptions#GP(0)#SS(0)#NM#MF#PF(fault-code)#AC(0)If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.If the DS, ES, FS, or GS register is used to access memory and it contains a null segmentselector.If a memory operand effective address is outside the SS segment limit.EM or TS in CR0 is set.If there is a pending x87 FPU exception.If a page fault occurs.If alignment checking is enabled and an unaligned memory reference is made while thecurrent privilege level is 3.Real-Address Mode Exceptions#GP#SS#NM#MFIf a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.If a memory operand effective address is outside the SS segment limit.EM or TS in CR0 is set.If there is a pending x87 FPU exception.Virtual-8086 Mode Exceptions#GP(0)#SS(0)#NM#MF#PF(fault-code)#AC(0)If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.If a memory operand effective address is outside the SS segment limit.EM or TS in CR0 is set.If there is a pending x87 FPU exception.If a page fault occurs.If alignment checking is enabled and an unaligned memory reference is made.Compatibility Mode ExceptionsSame as for protected mode exceptions.2-194 Vol. 1