Intel® Extended Memory 64 Technology Software Developer's Guide

BSR—Bit Scan ReverseOpcode Instruction 64-Bit Mode Compat/Leg DescriptionMode0F BD BSR r16,r/m16 Valid Valid Bit scan reverse on r/m160F BD BSR r32,r/m32 Valid Valid Bit scan reverse on r/m32REX.W + 0F BD BSR r64,r/m64 Valid N.E. Bit scan reverse on r/m64Flags AffectedThe ZF flag is set to 1 if all the source operand is 0; otherwise, the ZF flag is cleared. The CF, OF, SF, AF, and PF, flagsare undefined.IA-32e Mode OperationInstruction is promoted to 64-bits.Default Operation Size is 32 bitsEnables access to new registers R8-R15.Protected Mode Exceptions#GP(0)#SS(0)#PF(fault-code)#AC(0)If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.If the DS, ES, FS, or GS register contains a null segment selector.If a memory operand effective address is outside the SS segment limit.If a page fault occurs.If alignment checking is enabled and an unaligned memory reference is made while thecurrent privilege level is 3.Real-Address Mode Exceptions#GP#SSIf a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.If a memory operand effective address is outside the SS segment limit.Virtual-8086 Mode Exceptions#GP(0)#SS(0)#PF(fault-code)#AC(0)If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.If a memory operand effective address is outside the SS segment limit.If a page fault occurs.If alignment checking is enabled and an unaligned memory reference is made.Compatibility Mode ExceptionsSame as protected mode exceptions.64-Bit Mode Exceptions#SS(0)#GP(0)#PF(fault-code)#AC(0)If a memory address referencing the SS segment is in a non-canonical form.If the memory address is in a non-canonical form.If a page fault occurs.If alignment checking is enabled and an unaligned memory reference is made while thecurrent privilege level is 3.Vol. 1 2-45