Intel® Extended Memory 64 Technology Software Developer's Guide

FDIV/FDIVP/FIDIV—DivideOpcode Instruction 64-Bit Mode Compat/Leg DescriptionModeD8 /6 FDIV m32fp Valid Valid Divide ST(0) by m32fp and store result in ST(0)DC /6 FDIV m64fp Valid Valid Divide ST(0) by m64fp and store result in ST(0)D8 F0+i FDIV ST(0), ST(i) Valid Valid Divide ST(0) by ST(i) and store result in ST(0)DC F8+i FDIV ST(i), ST(0) Valid Valid Divide ST(i) by ST(0) and store result in ST(i)DE F8+i FDIVP ST(i), ST(0) Valid Valid Divide ST(i) by ST(0), store result in ST(i), andpop the register stackDE F9 FDIVP Valid Valid Divide ST(1) by ST(0), store result in ST(1), andpop the register stackDA /6 FIDIV m32int Valid Valid Divide ST(0) by m32int and store result in ST(0)DE /6 FIDIV m16int Valid Valid Divide ST(0) by m64int and store result in ST(0)IA-32e Mode OperationSame as legacy mode.FPU Flags AffectedC1Set to 0 if stack underflow occurred.Indicates rounding direction if the inexact-result exception (#P) is generated: 0 ← notroundup; 1 ← roundup.C0, C2, C3 Undefined.Floating-Point Exceptions#ISStack underflow occurred.#IAOperand is an SNaN value or unsupported format.±∞ / ±∞; ±0 / ±0#D Result is a denormal value.#Z DEST / ±0, where DEST is not equal to ±0.#U Result is too small for destination format.#O Result is too large for destination format.#P Value cannot be represented exactly in destination format.Protected Mode Exceptions#GP(0)#SS(0)#NM#MF#PF(fault-code)#AC(0)If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.If the DS, ES, FS, or GS register contains a null segment selector.If a memory operand effective address is outside the SS segment limit.EM or TS in CR0 is set.If there is a pending x87 FPU exception.If a page fault occurs.If alignment checking is enabled and an unaligned memory reference is made while thecurrent privilege level is 3.2-176 Vol. 1