Intel® Extended Memory 64 Technology Software Developer's Guide

ANDNPS—Bitwise Logical AND NOT of Packed Single-Precision Floating-PointValuesOpcode Instruction 64-Bit Mode Compat/Leg DescriptionMode0F 55 /r ANDNPS xmm1, xmm2/m128 Valid Valid Bitwise logical AND NOT of xmm2/m128 andxmm1.IA-32e Mode OperationEnables access to XMM8-XMM15.SIMD Floating-Point ExceptionsNone.Protected Mode Exceptions#GP(0)#SS(0)#PF(fault-code)#NM#UDFor an illegal memory operand effective address in the CS, DS, ES, FS or GS segments.If memory operand is not aligned on a 16-byte boundary, regardless of segment.For an illegal address in the SS segment.For a page fault.If TS in CR0 is set.If EM in CR0 is set.If OSFXSR in CR4 is 0.If CPUID feature flag SSE is 0.Real-Address Mode Exceptions#GP(0)#GP(0)#NM#UDIf memory operand is not aligned on a 16-byte boundary, regardless of segment.If any part of the operand lies outside the effective address space from 0 to FFFFH.If TS in CR0 is set.If EM in CR0 is set.If OSFXSR in CR4 is 0.If CPUID feature flag SSE is 0.Virtual-8086 Mode ExceptionsSame exceptions as in Real Address Mode#PF(fault-code)For a page fault.Compatibility Mode ExceptionsSame as protected mode exceptions.64-Bit Mode Exceptions#SS(0)#GP(0)If a memory address referencing the SS segment is in a non-canonical form.If the memory address is in a non-canonical form.If memory operand is not aligned on a 16-byte boundary, regardless of segment.Vol. 1 2-39