Intel® Extended Memory 64 Technology Software Developer's Guide

Table 2-8 CPUID Feature Information (Contd.)Reg.Bit # Mnemonic DescriptionEDX.3 PSE Page Size Extension. Large pages of size 4Mbyte are supported, includingCR4.PSE for controlling the feature, the defined dirty bit in PDE (PageDirectory Entries), optional reserved bit trapping in CR3, PDEs, and PTEs.EDX.4 TSC Time Stamp Counter. The RDTSC instruction is supported, includingCR4.TSD for controlling privilege.EDX.5 MSR Model Specific Registers RDMSR and WRMSR Instructions. The RDMSRand WRMSR instructions are supported. Some of the MSRs areimplementation dependent.EDX.6 PAE Physical Address Extension. Physical addresses greater than 32 bits aresupported: extended page table entry formats, an extra level in the pagetranslation tables is defined, 2 Mbyte pages are supported instead of 4 Mbytepages if PAE bit is 1. The actual number of address bits beyond 32 is notdefined, and is implementation specific.EDX.7 MCE Machine Check Exception. Exception 18 is defined for Machine Checks,including CR4.MCE for controlling the feature. This feature does not define themodel-specific implementations of machine-check error logging, reporting, andprocessor shutdowns. Machine Check exception handlers may have to dependon processor version to do model specific processing of the exception, or testfor the presence of the Machine Check feature.EDX.8 CX8 CMPXCHG8B Instruction. The compare-and-exchange 8 bytes (64 bits)instruction is supported (implicitly locked and atomic).EDX.9 APIC APIC On-Chip. The processor contains an Advanced Programmable InterruptController (APIC), responding to memory mapped commands in the physicaladdress range FFFE0000H to FFFE0FFFH (by default - some processorspermit the APIC to be relocated).EDX.10 Reserved ReservedEDX.11 SEP SYSENTER and SYSEXIT Instructions. The SYSENTER and SYSEXIT andassociated MSRs are supported.EDX.12 MTRR Memory Type Range Registers. MTRRs are supported. The MTRRcap MSRcontains feature bits that describe what memory types are supported, howmany variable MTRRs are supported, and whether fixed MTRRs aresupported.EDX.13 PGE PTE Global Bit. The global bit in page directory entries (PDEs) and page tableentries (PTEs) is supported, indicating TLB entries that are common to differentprocesses and need not be flushed. The CR4.PGE bit controls this feature.EDX.14 MCA Machine Check Architecture. The Machine Check Architecture, whichprovides a compatible mechanism for error reporting in Pentium 4 processors,P6 family processors, and future processors, is supported. The MCG_CAPMSR contains feature bits describing how many banks of error reporting MSRsare supported.EDX.15 CMOV Conditional Move Instructions. The conditional move instruction CMOV issupported. In addition, if x87 FPU is present as indicated by the CPUID.FPUfeature bit, then the FCOMI and FCMOV instructions are supportedEDX.16 PAT Page Attribute Table. Page Attribute Table is supported. This featureaugments the Memory Type Range Registers (MTRRs), allowing an operatingsystem to specify attributes of memory on a 4K granularity through a linearaddress.EDX.17 PSE-36 36-Bit Page Size Extension. Extended 4-MByte pages that are capable ofaddressing physical memory beyond 4 GBytes are supported. This featureindicates that the upper four bits of the physical address of the 4-MByte page isencoded by bits 13-16 of the page directory entry.EDX.18 PSN Processor Serial Number. The processor supports the 96-bit processoridentification number feature and the feature is enabled. (Only Pentium IIIprocessor supports this feature.)EDX.19 CLFSH CLFLUSH Instruction. CLFLUSH Instruction is supported.EDX.20 Reserved ReservedVol. 1 2-93